scholarly journals Generating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm

2011 ◽  
pp. 139-142
Author(s):  
Balasubramanian R ◽  
Goutham K ◽  
Jenitha S ◽  
Rahul R M ◽  
Thirupathie Raja B ◽  
...  
Keyword(s):  
Genetic Algorithm ◽  
Test Pattern ◽  
Complex Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Optimum Number ◽  
Automatic Test Pattern Generation ◽  
Combinational Circuits ◽  
Problem Space ◽  
Test Sets

In this paper we propose a method for the automatic test pattern generation for detecting multiple stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. The paper describes the GA and results obtained for the ISCAS 1989 benchmark circuits.

scholarly journals Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
S. Jayanthy ◽  
M. C. Bhuvaneswari ◽  
Keesarapalli Sujitha
Keyword(s):  
Test Generation ◽  
Power Dissipation ◽  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Automatic Test Pattern Generation ◽  
Delay Faults ◽  
Test Program ◽  
And Performance ◽  
Timing Behaviour

As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG) method based on a modified Fanout Oriented (FAN) to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM) based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.

scholarly journals Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 475-486
Author(s):  
Anshuman Chandra ◽  
Krishnendu Chakrabarty ◽  
Mark C. Hansen
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Testing Time ◽  
Automatic Test Pattern Generation ◽  
Test Quality ◽  
Efficient Test ◽  
Test Application ◽  
Test Sets ◽  
Test Architecture

We present novel test set encoding and pattern decompression methods for core-based systems. These are based on the use of twisted-ring counters and offer a number of important advantages–significant test compression (over 10X in many cases), less tester memory and reduced testing time, the ability to use a slow tester without compromising test quality or testing time, and no performance degradation for the core under test. Surprisingly, the encoded test sets obtained from partially-specified test sets (test cubes) are often smaller than the compacted test sets generated by automatic test pattern generation programs. Moreover, a large number of patterns are applied test-per-clock to cores, thereby increasing the likelihood of detecting non-modeled faults. Experimental results for the ISCAS benchmark circuits demonstrate that the proposed test architecture offers an attractive solution to the problem of achieving high test quality and low testing time with relatively slower, less expensive testers.

scholarly journals ATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm

2012 ◽  
pp. 255-260
Author(s):  
P. K. Chakrabarty ◽  
S. N. Patnaik
Keyword(s):  
Genetic Algorithm ◽  
Test Generation ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Automatic Test Pattern Generation ◽  
Delay Faults ◽  
And Performance ◽  
Test Vectors ◽  
Timing Behaviour

As design trends move toward nanometer technology, new Automatic Test Pattern Generation (ATPG)problems are merging. During design validation, the effect of crosstalk on reliability and performance cannot be ignored. So new ATPG Techniques has to be developed for testing crosstalk faults which affect the timing behaviour of circuits. In this paper, we present a Genetic Algorithm (GA) based test generation for crosstalk induced delay faults in VLSI circuits. The GA produces reduced test set which contains as few as possible test vector pairs, which detect as many as possible crosstalk delay faults. It uses a crosstalk delay fault simulator which computes the fitness of each test sequence. Tests are generated for ISCAS’85 and scan version of ISCAS’89 benchmark circuits. Experimental results demonstrate that GA gives higher fault coverage and compact test vectors for most of the benchmark circuits.

scholarly journals Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

2013 ◽  
pp. 42-47
Author(s):  
Monalisa Mohanty ◽  
S. N. Patnaik
Keyword(s):  
Integrated Circuits ◽  
Test Pattern ◽  
Difficult Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Automatic Test ◽  
Sequence Generation

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA).

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