A genetic algorithm for multiple fault model test generation for combinational VLSI circuits

1997 ◽  
Author(s):  
T. Arslan
Keyword(s):  
Genetic Algorithm ◽  
Model Test ◽  
Test Generation ◽  
Fault Model ◽  
Vlsi Circuits ◽  
Multiple Fault

scholarly journals ATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm

2012 ◽  
pp. 255-260
Author(s):  
P. K. Chakrabarty ◽  
S. N. Patnaik
Keyword(s):  
Genetic Algorithm ◽  
Test Generation ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Automatic Test Pattern Generation ◽  
Delay Faults ◽  
And Performance ◽  
Test Vectors ◽  
Timing Behaviour

As design trends move toward nanometer technology, new Automatic Test Pattern Generation (ATPG)problems are merging. During design validation, the effect of crosstalk on reliability and performance cannot be ignored. So new ATPG Techniques has to be developed for testing crosstalk faults which affect the timing behaviour of circuits. In this paper, we present a Genetic Algorithm (GA) based test generation for crosstalk induced delay faults in VLSI circuits. The GA produces reduced test set which contains as few as possible test vector pairs, which detect as many as possible crosstalk delay faults. It uses a crosstalk delay fault simulator which computes the fitness of each test sequence. Tests are generated for ISCAS’85 and scan version of ISCAS’89 benchmark circuits. Experimental results demonstrate that GA gives higher fault coverage and compact test vectors for most of the benchmark circuits.

scholarly journals Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Anand V. Hudli ◽  
Raghu V. Hudli
Keyword(s):  
Temporal Logic ◽  
Test Generation ◽  
Digital Circuits ◽  
Difficult Problem ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Temporal Behavior ◽  
Generation Algorithm

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

Generating test patterns for VLSI circuits using a genetic algorithm

1994 ◽  
Vol 30 (10) ◽  
pp. 778-779 ◽  
Author(s):  
M.J. O'Dare ◽  
T. Arslan
Keyword(s):  
Genetic Algorithm ◽  
Vlsi Circuits
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