scholarly journals ATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm

2012 ◽  
pp. 255-260
Author(s):  
P. K. Chakrabarty ◽  
S. N. Patnaik
Keyword(s):  
Genetic Algorithm ◽  
Test Generation ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Automatic Test Pattern Generation ◽  
Delay Faults ◽  
And Performance ◽  
Test Vectors ◽  
Timing Behaviour

As design trends move toward nanometer technology, new Automatic Test Pattern Generation (ATPG)problems are merging. During design validation, the effect of crosstalk on reliability and performance cannot be ignored. So new ATPG Techniques has to be developed for testing crosstalk faults which affect the timing behaviour of circuits. In this paper, we present a Genetic Algorithm (GA) based test generation for crosstalk induced delay faults in VLSI circuits. The GA produces reduced test set which contains as few as possible test vector pairs, which detect as many as possible crosstalk delay faults. It uses a crosstalk delay fault simulator which computes the fitness of each test sequence. Tests are generated for ISCAS’85 and scan version of ISCAS’89 benchmark circuits. Experimental results demonstrate that GA gives higher fault coverage and compact test vectors for most of the benchmark circuits.

scholarly journals Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
S. Jayanthy ◽  
M. C. Bhuvaneswari ◽  
Keesarapalli Sujitha
Keyword(s):  
Test Generation ◽  
Power Dissipation ◽  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Automatic Test Pattern Generation ◽  
Delay Faults ◽  
Test Program ◽  
And Performance ◽  
Timing Behaviour

As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG) method based on a modified Fanout Oriented (FAN) to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM) based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.

scholarly journals Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

2013 ◽  
pp. 42-47
Author(s):  
Monalisa Mohanty ◽  
S. N. Patnaik
Keyword(s):  
Integrated Circuits ◽  
Test Pattern ◽  
Difficult Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Automatic Test ◽  
Sequence Generation

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA).

scholarly journals Generating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm

2011 ◽  
pp. 139-142
Author(s):  
Balasubramanian R ◽  
Goutham K ◽  
Jenitha S ◽  
Rahul R M ◽  
Thirupathie Raja B ◽  
...  
Keyword(s):  
Genetic Algorithm ◽  
Test Pattern ◽  
Complex Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Optimum Number ◽  
Automatic Test Pattern Generation ◽  
Combinational Circuits ◽  
Problem Space ◽  
Test Sets

In this paper we propose a method for the automatic test pattern generation for detecting multiple stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. The paper describes the GA and results obtained for the ISCAS 1989 benchmark circuits.

scholarly journals Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

2020 ◽  
Vol 9 (2) ◽  
pp. 1673-1679
Keyword(s):  
Genetic Algorithm ◽  
Critical Path ◽  
Research Work ◽  
Propagation Delay ◽  
Vlsi Circuits ◽  
Delay Faults ◽  
Path Delay ◽  
Noise Margin ◽  
Critical Path Delay ◽  
Margin Propagation

FinFet transistors are used in major semiconductor organizations which play a significant role in the development of the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimisation of Critical path delay for sensitive test vector and no of iterations. The transfer characteristics curve is plotted along with the delay curve which helps in finding out the simulation parameters such as noise margin, propagation delay. The results in the methodology calculate the probability density function of the critical path by estimating mean, standard deviation and variance. The advantages of the integration of the two algorithms in this paper help in analyzing the specific faults in the circuits and the error correction of the broken link in the path analysis and has enhanced performance. Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this paper the research work on testing, diagnosis, estimation of Critical path and PDF of Critical path delay faults for FinFET based Combinational Circuits for 20nm and 32 nm Technologies are presented for the first time using latest Non Incremental Genetic algorithm.

scholarly journals Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies

2014 ◽  
Vol 8 (1) ◽  
pp. 77-83
Author(s):  
Pan Zhongliang ◽  
Chen Ling ◽  
Chen Yihui
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Circuits ◽  
Test Pattern ◽  
Average Power ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Delay Faults ◽  
High Power Consumption ◽  
Test Vectors

The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power consumption when compared with random test generation algorithm.

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