Increased breakdown voltage of silicon-on-insulator Schottky diodes

1993 ◽  
Vol 29 (15) ◽  
pp. 1381 ◽  
Author(s):  
B.R. Kang ◽  
S.N. Yoon ◽  
Y.H. Cho ◽  
S.I. Cha ◽  
Y.I. Choi
Keyword(s):  
Breakdown Voltage ◽  
Schottky Diodes ◽  
Silicon On Insulator

scholarly journals Implementation of a 900 V Switching Circuit for High Breakdown Voltage β-Ga2O3 Schottky Diodes

2019 ◽  
Vol 8 (7) ◽  
pp. Q3229-Q3234 ◽  
Author(s):  
Yen-Ting Chen ◽  
Jiancheng Yang ◽  
Fan Ren ◽  
Chin-Wei Chang ◽  
Jenshan Lin ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Schottky Diodes ◽  
Switching Circuit ◽  
High Breakdown Voltage

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

2021 ◽  
Author(s):  
Deivakani M ◽  
Sumithra M.G ◽  
Anitha P ◽  
Jenopaul P ◽  
Priyesh P. Gandhi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Impact Ionization ◽  
Semiconductor Industry ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Physical Models ◽  
Oxide Semiconductor ◽  
Soi Mosfet ◽  
P Type ◽  
Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

High Voltage Silicon Carbide Devices

1998 ◽  
Vol 512 ◽  
Author(s):  
B. Jayant Baliga
Keyword(s):  
Silicon Carbide ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Impact Ionization ◽  
Voltage Drop ◽  
Schottky Diodes ◽  
Inversion Layer ◽  
Drift Region ◽  
Edge Termination ◽  
Silicon Devices

ABSTRACTProgress made in the development of high performance power rectifiers and switches from silicon carbide are reviewed with emphasis on approaching the 100-fold reduction in the specific on-resistance of the drift region when compared with silicon devices with the same breakdown voltage. The highlights are: (a) Recently completed measurements of impact ionization coefficients in SiC indicate an even higher Baliga's figure of merit than projected earlier. (b) The commonly reported negative temperature co-efficient for breakdown voltage in SiC devices has been shown to arise at defects, allaying concerns that this may be intrinsic to the material. (c) Based upon fundamental considerations, it has been found that Schottky rectifiers offer superior on-state voltage drop than P-i-N rectifiers for reverse blocking voltages below 3000 volts. (d) Nearly ideal breakdown voltage has been experimentally obtained for Schottky diodes using an argon implanted edge termination. (e) Planar ion-implanted junctions have been successfully fabricated using oxide as a mask with high breakdown voltage and low leakage currents by using a filed plate edge termination. (f) High inversion layer mobility has been experimentally demonstrated on both 6H and 4H-SiC by using a deposited oxide layer as gate dielectric. (g) A novel, high-voltage, normally-off, accumulation-channel, MOSFET has been proposed and demonstrated with 50x lower specific on-resistance than silicon devices in spite of using logic-level gate drive voltages. These results indicate that SiC based power devices could become commercially viable in the 21st century if cost barriers can be overcome.

scholarly journals Device Design Assessment of GaN Merged P-i-N Schottky Diodes

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1550 ◽  
Author(s):  
Yuliang Zhang ◽  
Xing Lu ◽  
Xinbo Zou
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Schottky Diodes ◽  
Schottky Contact ◽  
Background Concentration ◽  
Model Parameters ◽  
Design Assessment ◽  
Blocking Voltage ◽  
Aided Design ◽  
Drift Layer

Device characteristics of GaN merged P-i-N Schottky (MPS) diodes were evaluated and studied via two-dimensional technology computer-aided design (TCAD) after calibrating model parameters and critical electrical fields with experimental proven results. The device’s physical dimensions and drift layer concentration were varied to study their influence on the device’s performance. Extending the inter-p-GaN region distance or the Schottky contact portion could enhance the forward conduction capability; however, this leads to compromised electrical field screening effects from neighboring PN junctions, as well as reduced breakdown voltage. By reducing the drift layer background concentration, a higher breakdown voltage was expected for MPSs, as a larger portion of the drift layer itself could be depleted for sustaining vertical reverse voltage. However, lowering the drift layer concentration would also result in a reduction in forward conduction capability. The method and results of this study provide a guideline for designing MPS diodes with target blocking voltage and forward conduction at a low bias.

scholarly journals GaN Micropillar Schottky Diodes with High Breakdown Voltage Fabricated by Selective‐Area Growth

2019 ◽  
Vol 217 (7) ◽  
pp. 1900676
Author(s):  
Arne Debald ◽  
Simon Kotzea ◽  
Jona Riedel ◽  
Michael Heuken ◽  
Holger Kalisch ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Schottky Diodes ◽  
Selective Area Growth ◽  
High Breakdown Voltage ◽  
Selective Area ◽  
Area Growth

Temperature Stability of Breakdown Voltage on SiC Power Schottky Diodes with Different Barrier Heights

2005 ◽  
Vol 483-485 ◽  
pp. 933-936 ◽  
Author(s):  
R. Pierobon ◽  
G. Meneghesso ◽  
E. Zanoni ◽  
Fabrizio Roccaforte ◽  
Francesco La Via ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Schottky Diodes ◽  
Electrical Characterization ◽  
Temperature Stability ◽  
Voltage Versus ◽  
Good Thermal Stability ◽  
Barrier Heights ◽  
Schottky Rectifiers ◽  
Reverse Recovery Time

The static and dynamic electrical characterization of power Schottky rectifiers both with Ti and Ni2Si as Schottky metals having low negative coefficient of the breakdown voltage versus temperature will be presented in this paper. The values of the barrier height are respectively 1.28eV and 1.68eV, as extracted using the Tung’s model for inhomogeneous contacts from forward currentvoltage characteristics. These values were found to be in good agreement with those obtained by means of capacitance-voltage measurements. The breakdown voltage shows an almost linear dependence from the temperature for both types of devices. The extracted coefficients are respectively -0.08V/°C and -0.11V/°C, thus guarantying stable and reliable behaviour. Very short reverse recovery time at RT and at 125°C confirms the good thermal stability of these devices.

Suppress of Substrate-Assisted Depletion Effects in Super Junction LDMOS on Thin Film SOI

2013 ◽  
Vol 721 ◽  
pp. 521-526
Author(s):  
Chao Xia ◽  
Xin Hong Cheng ◽  
Zhong Jian Wang ◽  
Da Wei He ◽  
Duo Cao ◽  
...  
Keyword(s):  
Charge Density ◽  
Breakdown Voltage ◽  
Inversion Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Device Structure ◽  
Depletion Effect ◽  
Fabrication Procedure ◽  
A Charge

Conventional super-junction lateral double diffused MOSFET (SJ-LDMOS) fabricated on Silicon on Insulator (SOI) substrate suffers from low breakdown voltage under the same on-resistance due to substrate-assisted depletion effect. To suppress this effect, it is important to find the charge density in the inversion layer under buried oxide. In this paper, we propose a charge density equation and its formulation. The results were used in a 3D device simulator to optimize the device structure. The experimental results confirm that the equation is useful to optimize device performance. The breakdown voltage of structure increased 54% and on-state-resistance decreased 58% compared to conventional SJ device. The device fabrication procedure is fully compatible with mainstream SOI CMOS process.

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