GaAs MESFETs, ring oscillators and divide-by-2 integrated circuits fabricated on MBE grown GaAs on Si substrates

1988 ◽  
Vol 24 (16) ◽  
pp. 1037 ◽  
Author(s):  
F. Ren ◽  
N. Chand ◽  
P. Garbinski ◽  
S.J. Pearton ◽  
C.S. Wu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Ring Oscillators ◽  
Si Substrates ◽  
Gaas On Si

Epitaxial GaAs on Si: Progress and Potential Applications

1987 ◽  
Vol 91 ◽  
Author(s):  
Don W. Shaw
Keyword(s):  
Integrated Circuits ◽  
Low Cost ◽  
Epitaxial Structure ◽  
Epitaxial Gaas ◽  
Si Substrates ◽  
Gaas On Si ◽  
Potential Applications ◽  
The Individual ◽  
First Time ◽  
Realistic Appraisal

ABSTRACTRecent successes, such as the demonstration of a 1K SRAM, have established epitaxial GaAs on Si substrates as a promising technology rather than a device designer's dream. For the first time we can seriously consider combining the individual electronic and optical properties of GaAs and Si within a single epitaxial structure. Applications for GaAs on Si range from those that simply utilize the Si as a low-cost, large-areapassive substrate with superior strength and thermal conductivity to the long-sought multifunction integrated circuits where Si and III–V components are integrated within a single monolithic chip. This paper will attempt to provide a realistic appraisal of the potential applications of epitaxial GaAs on Si with emphasis on the special demands imposed by each application and barriers that must be circumvented.

scholarly journals Experimental Study on the Thickness-Dependent Hardness of SiO2 Thin Films Using Nanoindentation

Coatings ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 23
Author(s):  
Weiguang Zhang ◽  
Jijun Li ◽  
Yongming Xing ◽  
Xiaomeng Nie ◽  
Fengchao Lang ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Grain Size ◽  
Integrated Circuits ◽  
Film Thickness ◽  
Depth Range ◽  
Micro Electro Mechanical Systems ◽  
Si Substrates ◽  
Sio2 Thin Film ◽  
Average Grain Size

SiO2 thin films are widely used in micro-electro-mechanical systems, integrated circuits and optical thin film devices. Tremendous efforts have been devoted to studying the preparation technology and optical properties of SiO2 thin films, but little attention has been paid to their mechanical properties. Herein, the surface morphology of the 500-nm-thick, 1000-nm-thick and 2000-nm-thick SiO2 thin films on the Si substrates was observed by atomic force microscopy. The hardnesses of the three SiO2 thin films with different thicknesses were investigated by nanoindentation technique, and the dependence of the hardness of the SiO2 thin film with its thickness was analyzed. The results showed that the average grain size of SiO2 thin film increased with increasing film thickness. For the three SiO2 thin films with different thicknesses, the same relative penetration depth range of ~0.4–0.5 existed, above which the intrinsic hardness without substrate influence can be determined. The average intrinsic hardness of the SiO2 thin film decreased with the increasing film thickness and average grain size, which showed the similar trend with the Hall-Petch type relationship.

GaAs/AlGaAs quantum-well infrared photodetectors on GaAs-on-Si substrates

1997 ◽  
Vol 71 (1) ◽  
pp. 78-80 ◽  
Author(s):  
D. K. Sengupta ◽  
W. Fang ◽  
J. I. Malin ◽  
J. Li ◽  
T. Horton ◽  
...  
Keyword(s):  
Quantum Well ◽  
Infrared Photodetectors ◽  
Si Substrates ◽  
Quantum Well Infrared Photodetectors ◽  
Gaas On Si

Minority Carrier Diffusion Length Improvement in Czochralski Silicon by Aluminum Gettering

1995 ◽  
Vol 378 ◽  
Author(s):  
Subhash M. Joshi ◽  
Ylrich M. GÖsele ◽  
Teh Y. Tan
Keyword(s):  
Solar Cell ◽  
Integrated Circuits ◽  
Minority Carrier ◽  
Minority Carrier Diffusion Length ◽  
Carrier Diffusion ◽  
Solar Cell Efficiency ◽  
Czochralski Silicon ◽  
Si Substrates ◽  
Cell Efficiency ◽  
Si Wafer

AbstractGettering is widely used for fabricating integrated circuits using Si substrates, and has great potential for solar cell fabrications as well. Recently available solar cell efficiency studies have shown the benefits of the wafer backside Al, attributable to effects of gettering, a wafer backside field, and passivation of grain boundaries and dislocations. In this paper, we report experimental results which showed unambiguously that Czochralski Si wafer bulk minority carrier diffusion lengths can be significantly improved due to gettering of impurities by wafer backside Al, which also provided a protection from environmental contamination.

IVA-3 GaAs/AlGaAs heterojunction emitter-down bipolar circuits fabricated on GaAs-on-Si substrates

1987 ◽  
Vol 34 (11) ◽  
pp. 2369-2370
Author(s):  
L.T. Tran ◽  
R.J. Matyi ◽  
H. Shichijo ◽  
H.-T. Yuan ◽  
J.W. Lee
Keyword(s):  
Si Substrates ◽  
Gaas On Si

LOW-Temperature Epitaxial Growth of GaAs on Si Substrates by MBE

1992 ◽  
Vol 263 ◽  
Author(s):  
Ting-Yen Chiang ◽  
En-Huery Liu ◽  
Der-Hwa Yiin ◽  
Tri-Rung Yew
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Low Temperature ◽  
Epitaxial Growth ◽  
Defect Density ◽  
Solution Treatment ◽  
Plan View ◽  
Si Substrates ◽  
Gaas On Si ◽  
Transmission Electron

ABSTRACTThis paper presents results of the low—temperature epitaxial growth of GaAs on Si substrates with orientation 1°—4° off (100) by molecular beam epitaxy (MBE). The epitaxial growth ·is carried out on Si wafers subjected to HF solution treatment by “spin-etch” technique before the wafer is transferred to the entry chamber of MBE system. Methods used for reducing defect density in the epitaxial layers are proposed. The characterization techniques include cross-sectional transmission electron microscopy (XTEM), plan-view transmission electron microscopy, scanning electron microscopy (S EM), and double crystal X-ray diffraction (DCXRD). Epitaxial films with a full width at half—maximum (FWHM) of about 310 arcsec measured by DCXRD are obtained without annealing.-

Probing Semiconductor/Insulator Heterostructures Through Electron Spin Resonance of Point Defects: Interfaces, Interlayers, and Stress

2006 ◽  
Vol 984 ◽  
Author(s):  
A. Stesmans ◽  
K. Clémer ◽  
P. Somers ◽  
V. V. Afanas'ev
Keyword(s):  
Electron Spin Resonance ◽  
Integrated Circuits ◽  
Electron Spin ◽  
Point Defects ◽  
Atomic Scale ◽  
Interface Quality ◽  
Si Substrates ◽  
Spin Resonance ◽  
The Impact

AbstractElectron spin resonance (ESR) spectroscopy has become indispensable when it comes to the characterization on atomic-scale of structural, and correlated, electrical properties of actual semiconductor/insulator heterostructures. Through probing of paramagnetic point defects such as the Pb-type defects, E', and EX as a function of VUV irradiation and post deposition heat treatment, basic information as to the nature, quality, and thermal stability of the interface and interfacial regions can be established. This is illustrated by some specific examples of ESR analysis on contemporary Si/insulator structures promising for future developments in integrated circuits. First the impact of strain on the Si/SiO2 entity will be discussed. Through ESR analysis of thermally oxidized (111)Si substrates mechanically stressed in situ during oxidation, and tensile strained (100)sSi/SiO2 structures, it will be pointed out that in-plane tensile stress in Si can significantly improve the interface quality. Next, ESR results for stacks of (100)Si/SiOx/HfO2 and (100)Si/LaAlO3 are presented, revealing the potential to attain a high quality Si/SiO2 interface for the former and an abrupt, thermally stable interface for the latter.

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