CMOS circuits made in lamp-recrystallised silicon-on-insulator

1984 ◽  
Vol 20 (7) ◽  
pp. 298 ◽  
Author(s):  
D.P. Vu ◽  
C. Leguet ◽  
M. Haond ◽  
D. Bensahel ◽  
J.P. Colinge
Keyword(s):  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Made In

50 GHz S-shaped rat-race balun with 1.4 dB insertion loss in a wafer-level chip-size package process

2009 ◽  
Vol 1 (4) ◽  
pp. 347-352
Author(s):  
Ahmet Oncu ◽  
Chiaki Inui ◽  
Yasuo Manzawa ◽  
Minoru Fujishima
Keyword(s):  
Integrated Circuits ◽  
Insertion Loss ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Wafer Level ◽  
Chip Area ◽  
The Core ◽  
Chip Size ◽  
Differential Circuits ◽  
On Chip

In millimeter-wave CMOS circuits, a balun is useful for connecting off-chip single-end devices and on-chip differential circuits to improve noise immunity. However, an on-chip balun occupies a large chip area. To reduce the chip area required for the on-chip balun, a new rat-race balun using a rewiring technology with a wafer-level chip-size package (W-CSP) is proposed. The W-CSP balun occupies no area in a die because it is placed over integrated circuits. In the proposed balun, an S-shaped structure is adopted in order to directly connect the balun to differential GSGSG pads on a chip with a small area. The S-shaped W-CSP balun was fabricated on a silicon-on-insulator (SOI) substrate. The core area of the S-shaped rat-race balun is 480×735 µm, which is 22.4% that of a square rat-race balun. As a result of measurement, we found that the minimum insertion loss is 1.4 dB and the operating frequency ranges from 40 to 61 GHz.

Characteristics of SOI CMOS circuits made in n/n+/n oxidised porous silicon structures

1986 ◽  
Vol 22 (24) ◽  
pp. 1291 ◽  
Author(s):  
K. Barla ◽  
G. Bomchil ◽  
R. Herino ◽  
A. Monroy ◽  
Y. Gris
Keyword(s):  
Porous Silicon ◽  
Cmos Circuits ◽  
Silicon Structures ◽  
Made In ◽  
Soi Cmos

A lateral COMFET made in thin silicon-on-insulator film

1986 ◽  
Vol 7 (12) ◽  
pp. 697-699 ◽  
Author(s):  
J.-P. Colinge ◽  
Shang-Yi Chiang
Keyword(s):  
Silicon On Insulator ◽  
Insulator Film ◽  
Thin Silicon ◽  
Made In

Improved Soi Films By High Dose Oxygen Implantation and Lamp Annealing

1985 ◽  
Vol 53 ◽  
Author(s):  
G. K. Celler ◽  
P. L. F. Hemment ◽  
K. W. West ◽  
J. M. Gibson
Keyword(s):  
High Speed ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
High Dose ◽  
Cmos Circuits ◽  
Radiation Hardened ◽  
Silicon On Insulator Technology ◽  
Annealing Procedure ◽  
Oxygen Precipitates ◽  
Sharp Interfaces

ABSTRACTIon beam synthesis of a buried SiO2 layer is an attractive silicon-on-insulator technology for high speed CMOS circuits and radiation hardened devices. We demonstrate here a new annealing procedure at 1405°C that produces silicon films of excellent quality, essentially free of oxygen precipitates and with sharp interfaces between the Si and the SiO2.

CMOS circuits made in thin SIMOX films

1987 ◽  
Vol 23 (21) ◽  
pp. 1162 ◽  
Author(s):  
J.P. Colinge ◽  
T.I. Kamins
Keyword(s):  
Cmos Circuits ◽  
Made In

scholarly journals Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

2021 ◽  
Vol 10 (6) ◽  
pp. 1-10
Author(s):  
S.C. Wagaj ◽  
◽  
S.C. Patil ◽  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
Junctionless Transistor ◽  
Dual Gate ◽  
Static Power

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

Laser Recrystallization and 3D Integration

1984 ◽  
Vol 35 ◽  
Author(s):  
J.P. Colinge
Keyword(s):  
Single Crystal ◽  
Grain Boundaries ◽  
High Speed ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
3D Integration ◽  
Stages Of Development ◽  
3D Ics ◽  
Laser Recrystallization ◽  
Integrated Structures

ABSTRACTThere are various methods for producing device-worthy Silicon-on-Insulator films, most, however, are unsuitable for fabrication of 3D integrated structures. The laser recrystallization technique is currently the only one which has produced single-crystal devices for 3D ICs. Improvements on this technique have been such that defects such as grain boundaries can be localized and even eliminated. High speed CMOS circuits with VLSI features have been realized as well as new devices which take advantage of the 3D arrangement of vertically integrated structures. Although 3D integration is still in the early stages of development, it has already opened up new perspectives for applications such as high speed circuits, dense memories, and sensors.

Erratum: CMOS circuits made in thin SIMOX films

1987 ◽  
Vol 23 (25) ◽  
pp. 1397
Author(s):  
J.P. Colinge ◽  
T.I. Kamins
Keyword(s):  
Cmos Circuits ◽  
Made In
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