Flexible Single-Crystalline GaN Substrate by Direct Deposition of III-N Thin Films on Polycrystalline Metal Tape

2021 ◽  
Author(s):  
Shahab Shervin ◽  
Mina Moradnia ◽  
Md Kamrul Alam ◽  
Tian Tong ◽  
Mi-Hee Ji ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Flexible Electronics ◽  
Cost Reduction ◽  
Semiconductor Materials ◽  
Manufacturing Cost ◽  
Device Performance ◽  
Polycrystalline Metal ◽  
Group Iii ◽  
Device Stability ◽  
Metal Tape

Flexible electronics and mechanically bendable devices based on Group III-N semiconductor materials are emerging, while there are several challenges in manufacturing-cost reduction, device stability and flexibility, and device-performance improvement. To...

Applications of MeV Ion Implantation in Semiconductor Device Manufacturing

1994 ◽  
Vol 354 ◽  
Author(s):  
John O. Borland
Keyword(s):  
Ion Implantation ◽  
Flash Memory ◽  
Mass Production ◽  
Cost Reduction ◽  
Semiconductor Device ◽  
Design Rule ◽  
Great Promise ◽  
Manufacturing Cost ◽  
Device Performance ◽  
The World

AbstractUse of MeV ion implantation for mass production of CMOS devices at 0.5um design rule and beyond is now being accepted around the world for 16Mb DRAM, 16Mb Flash memory and CMOS logic/microprocessor technologies. Incorporating MeV well formation for twin well and triple well results in a reduction of up to 3 masking layers corresponding to process simplification and manufacturing cost reduction of 10% to 16%. For CMOS logic application, a new structure called BILLI (Buriedjmplanted Layer for Lateral Isolation) is showing great promise for latch-up free CMOS and when combined with hydrogen denuded bulk Czochraliski (CZ) grown silicon wafers, has the potential to replace epitaxial wafers with improved device performance. This paper will review MeV ion implantation use for these various CMOS applications.

A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing

2006 ◽  
Vol 913 ◽  
Author(s):  
Young Way Teh ◽  
John Sudijono ◽  
Alok Jain ◽  
Shankar Venkataraman ◽  
Sunder Thirupapuliyur ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Dielectric Film ◽  
High Stress ◽  
Significant Degree ◽  
Strain Effect ◽  
Device Performance ◽  
Hot Carrier ◽  
Tcad Simulation ◽  
Improve Device ◽  
Deposition Techniques

AbstractThis work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

Investigations on Dynamic Puncture Behaviors of Integrated Composite Reinforced with Varying Fabrics

2013 ◽  
Vol 365-366 ◽  
pp. 1070-1073 ◽  
Author(s):  
Chia Chang Lin ◽  
Ting Ting Li ◽  
Ching Wen Lou ◽  
Jan Yi Lin ◽  
Jia Horng Lin
Keyword(s):  
Performance Improvement ◽  
Cost Reduction ◽  
Body Armor ◽  
Packaging Materials ◽  
Puncture Resistance ◽  
Fabric Reinforcement ◽  
Number Of Layers ◽  
Layer Composite ◽  
Puncture Force ◽  
And Performance

The dynamic puncture resistance of multi-layer integrated composite which was comprised of glass fabric reinforcement or Kevlar fabric reinforcement and nonwovens were discussed as related to recycled Kevlar fibers amount, number of layer and K-ply position for purpose of cost reduction and performance improvement. The result shows that, 20 wt% Kevlar fibers contained in nonwovens have the optimum puncture resistance. And the dynamic puncture force increases linearly with number of layers, and also improves proportionally as increasing number of K-ply. The resultant multi-layer composite is expected to be used as body armor interlayer and packaging materials.

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Short Circuit ◽  
Effective Means ◽  
Gate Oxide ◽  
Device Performance ◽  
High Concentration ◽  
Safe Operation ◽  
Major Drawback ◽  
Oxide Reliability ◽  
Conventional Device

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

A Novel Approach to Control Source/Drain Cavity Profile for Device Performance Improvement

2018 ◽  
Vol 65 (9) ◽  
pp. 3640-3645 ◽  
Author(s):  
Hsien-Ching Lo ◽  
Jianwei Peng ◽  
Edward Reis ◽  
Baofu Zhu ◽  
Wei Ma ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Device Performance ◽  
Novel Approach ◽  
Cavity Profile ◽  
Control Source
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