Device Performance Improvement of PMOS Devices Fabricated by $\hbox{B}_{2}\hbox{H}_{6}$ PIII/PLAD Processing

2007 ◽  
Vol 54 (9) ◽  
pp. 2497-2502 ◽  
Author(s):  
Shu Qin ◽  
A. McTeer
Keyword(s):  
Performance Improvement ◽  
Device Performance

A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing

2006 ◽  
Vol 913 ◽  
Author(s):  
Young Way Teh ◽  
John Sudijono ◽  
Alok Jain ◽  
Shankar Venkataraman ◽  
Sunder Thirupapuliyur ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Dielectric Film ◽  
High Stress ◽  
Significant Degree ◽  
Strain Effect ◽  
Device Performance ◽  
Hot Carrier ◽  
Tcad Simulation ◽  
Improve Device ◽  
Deposition Techniques

AbstractThis work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Short Circuit ◽  
Effective Means ◽  
Gate Oxide ◽  
Device Performance ◽  
High Concentration ◽  
Safe Operation ◽  
Major Drawback ◽  
Oxide Reliability ◽  
Conventional Device

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

A Novel Approach to Control Source/Drain Cavity Profile for Device Performance Improvement

2018 ◽  
Vol 65 (9) ◽  
pp. 3640-3645 ◽  
Author(s):  
Hsien-Ching Lo ◽  
Jianwei Peng ◽  
Edward Reis ◽  
Baofu Zhu ◽  
Wei Ma ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Device Performance ◽  
Novel Approach ◽  
Cavity Profile ◽  
Control Source

Device performance improvement of InGaP/InGaAs doped-channel FETs

2005 ◽  
Vol 26 (12) ◽  
pp. 861-863 ◽  
Author(s):  
Feng-Tso Chien ◽  
Jin-Mu Yin ◽  
Hsien-Chin Chiu ◽  
Yi-Jen Chan
Keyword(s):  
Performance Improvement ◽  
Device Performance

Device Performance Improvement Based on Transient Enhanced Diffusion Suppression in the Deep Sub-Quarter Micron Scale

2000 ◽  
Vol 39 (Part 1, No. 4B) ◽  
pp. 2172-2176
Author(s):  
Hyun-Sik Kim ◽  
Jong-Hyon Ahn ◽  
Duk-Min Lee ◽  
Kwang-Dong Yoo ◽  
Soo-Cheol Lee ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Device Performance ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion

Device performance improvement with Nitrogen implanted during LDD sequence

2007 ◽  
Author(s):  
N. Auriac ◽  
C. Laviron ◽  
N. Cagnat ◽  
J. Singer ◽  
B. Duriez ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Device Performance
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