Turning on/off satellite droplet ejection for flexible sample delivery on digital microfluidics

Lab on a Chip ◽  
2020 ◽  
Vol 20 (20) ◽  
pp. 3709-3719
Author(s):  
Haoran Li ◽  
Ren Shen ◽  
Cheng Dong ◽  
Tianlan Chen ◽  
Yanwei Jia ◽  
...  

Convenient electric control and electrode design allow flexible sample delivery on-chip in a wide range on microfluidics.

Lab on a Chip ◽  
2021 ◽  
Author(s):  
Jiao Zhai ◽  
Caiwei Li ◽  
Haoran Li ◽  
Shuhong Yi ◽  
Ning Yang ◽  
...  

Microfluidics has been the most promising platform for drug screening with a limited number of cells. However, convenient on-chip preparation of a wide range of drug concentrations remains a large...


Energies ◽  
2019 ◽  
Vol 12 (11) ◽  
pp. 2204 ◽  
Author(s):  
Muhammad Fahad ◽  
Arsalan Shahid ◽  
Ravi Reddy Manumachu ◽  
Alexey Lastovetsky

Energy of computing is a serious environmental concern and mitigating it is an important technological challenge. Accurate measurement of energy consumption during an application execution is key to application-level energy minimization techniques. There are three popular approaches to providing it: (a) System-level physical measurements using external power meters; (b) Measurements using on-chip power sensors and (c) Energy predictive models. In this work, we present a comprehensive study comparing the accuracy of state-of-the-art on-chip power sensors and energy predictive models against system-level physical measurements using external power meters, which we consider to be the ground truth. We show that the average error of the dynamic energy profiles obtained using on-chip power sensors can be as high as 73% and the maximum reaches 300% for two scientific applications, matrix-matrix multiplication and 2D fast Fourier transform for a wide range of problem sizes. The applications are executed on three modern Intel multicore CPUs, two Nvidia GPUs and an Intel Xeon Phi accelerator. The average error of the energy predictive models employing performance monitoring counters (PMCs) as predictor variables can be as high as 32% and the maximum reaches 100% for a diverse set of seventeen benchmarks executed on two Intel multicore CPUs (one Haswell and the other Skylake). We also demonstrate that using inaccurate energy measurements provided by on-chip sensors for dynamic energy optimization can result in significant energy losses up to 84%. We show that, owing to the nature of the deviations of the energy measurements provided by on-chip sensors from the ground truth, calibration can not improve the accuracy of the on-chip sensors to an extent that can allow them to be used in optimization of applications for dynamic energy. Finally, we present the lessons learned, our recommendations for the use of on-chip sensors and energy predictive models and future directions.


2019 ◽  
Vol 6 (4) ◽  
pp. 95 ◽  
Author(s):  
Christina Kryou ◽  
Valentina Leva ◽  
Marianneza Chatzipetrou ◽  
Ioanna Zergioti

Bioprinting techniques can be used for the in vitro fabrication of functional complex bio-structures. Thus, extensive research is being carried on the use of various techniques for the development of 3D cellular structures. This article focuses on direct writing techniques commonly used for the fabrication of cell structures. Three different types of bioprinting techniques are depicted: Laser-based bioprinting, ink-jet bioprinting and extrusion bioprinting. Further on, a special reference is made to the use of the bioprinting techniques for the fabrication of 2D and 3D liver model structures and liver on chip platforms. The field of liver tissue engineering has been rapidly developed, and a wide range of materials can be used for building novel functional liver structures. The focus on liver is due to its importance as one of the most critical organs on which to test new pharmaceuticals, as it is involved in many metabolic and detoxification processes, and the toxicity of the liver is often the cause of drug rejection.


2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Johanna Sepulveda ◽  
Ricardo Pires ◽  
Guy Gogniat ◽  
Wang Jiang Chau ◽  
Marius Strum

As electronic systems are pervading our lives, MPSoC (multiprocessor system-on-chip) security is becoming an important requirement. MPSoCs are able to support multiple applications on the same chip. The challenge is to provide MPSoC security that makes possible a trustworthy system that meets the performance and security requirements of all the applications. The network-on-chip (NoC) can be used to efficiently incorporate security. Our work proposes the implementation of QoSS (quality of security service) to overcome present MPSoC vulnerabilities. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. QoSS takes advantage of the NoC wide system visibility and critical role in enabling system operation, exploiting the NoC components to detect and prevent a wide range of attacks. In this paper, we present the implementation of a layered dynamic security NoC architecture that integrates agile and dynamic security firewalls in order to detect attacks based on different security rules. We evaluate the effectiveness of our approach over several MPSoCs scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of different security policies for several MPSoC applications.


Author(s):  
Neelufar Naheed Saudagar ◽  
◽  
Seema Deshmukh

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