High Performance Flexible Organic Phototransistors with Ultrashort Channel Length

ACS Photonics ◽  
2018 ◽  
Vol 5 (9) ◽  
pp. 3712-3722 ◽  
Author(s):  
Jianfeng Zhong ◽  
Xiaomin Wu ◽  
Shuqiong Lan ◽  
Yuan Fang ◽  
Huipeng Chen ◽  
...  
Nano Letters ◽  
2021 ◽  
Author(s):  
Jakob Lenz ◽  
Anna Monika Seiler ◽  
Fabian Rudolf Geisenhof ◽  
Felix Winterer ◽  
Kenji Watanabe ◽  
...  

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.


2021 ◽  
Author(s):  
Anubha Bilgaiyan ◽  
Seung-Il Cho ◽  
Miho Abiko ◽  
Kaori Watanabe ◽  
Makoto Mizukami

Abstract The low mobility and large contact resistance in organic thin-film transistors (OTFTs) are the two major limiting factors in the development of high-performance organic logic circuits. Here, solution-processed high-performance OTFTs and circuits are reported with a polymeric gate dielectric and 6,6 bis (trans-4-butylcyclohexyl)-dinaphtho[2,1-b:2,1-f ]thieno[3,2-b]thiophene (4H-21DNTT) for the organic semiconducting layer. By optimizing and controlling the fabrication conditions, a record high saturation mobility of 8.8 cm2V− 1s− 1 was demonstrated as well as large on/off ratios (> 106) for relatively short channel lengths of 15 µm and an average carrier mobility of 10.5 cm2V-1s-1 for long channel length OTFTs (> 50 µm). The pseudo-CMOS inverter circuit with a channel length of 15 µm exhibited sharp switching characteristics with a high signal gain of 31.5 at a supply voltage of 20 V. In addition to the inverter circuit, NAND logic circuits were further investigated, which also exhibited remarkable logic characteristics, with a high gain, an operating frequency of 5 kHz, and a short propagation delay of 22.1 µs. The uniform and reproducible performance of 4H-21DNTT OTFTs show potential for large-area, low-cost real-world applications on industry-compatible bottom-contact substrates.


2020 ◽  
Vol 12 (44) ◽  
pp. 49915-49925
Author(s):  
Yujie Yan ◽  
Qizhen Chen ◽  
Xiaomin Wu ◽  
Xiumei Wang ◽  
Enlong Li ◽  
...  

2000 ◽  
Vol 621 ◽  
Author(s):  
Min-Cheol Lee ◽  
Juhn-Suk Yoo ◽  
Kee-Chan Park ◽  
Sang-Hoon Jung ◽  
Min-Koo Han ◽  
...  

ABSTRACTWe have proposed and fabricated a new poly-Si TFT that employs selectively doped regions between the source and drain in order to reduce leakage current without the sacrifice of the on current. In the proposed poly-Si TFTs, the selectively doped regions where doping concentration is identical to that of source/drain, reduce the effective channel length during the on state. Under the off state, the selectively doped regions may reduce the lateral electric field induced in the depletion region near drain so that the leakage current reduces considerably. The experimental data of the proposed TFT shows that it has the high on-current, low leakage current and low threshold voltage when compared with conventional TFT. The fabrication steps for the proposed TFT are reduced because ion-implantation for source/drain and selectively doped regions is performed simultaneously prior to an excimer laser irradiation. It should be noted that, in the proposed TFT, only one excimer laser annealing is required while two excimer laser annealing steps are required in conventional TFT.


The down scaling of Meatal Oxide Semiconductor Field Effect transistor (MOSFET) devices nevertheless the most important and effective way for accomplishing high performance with low power adopted the miniaturization trend of channel length from the past, which is very aggressive. The double gate NanoFET with the incorporation of the strain Silicon technology is developed here on 45nm gate length comprises of tri-layered (s-Si/s-SiGe/s-Si) channel region with varied thicknesses. The induction of strain increases mobility of charge carriers. Two gates are deployed in bottom and up side of strained channel provides better control over the depletion region developed by applying same gate bias voltage. This newly developed double gate NanoFET on 45nm channel length provides 63% reduced subthreshold leakage current, and maximum electron drift velocity in strained channel.


2018 ◽  
Vol 166 (3) ◽  
pp. A5244-A5251 ◽  
Author(s):  
Byong-June Lee ◽  
Hyean-Yeol Park ◽  
Dae-Soo Yang ◽  
Tong-Hyun Kang ◽  
Seongpil Hwang ◽  
...  

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740069 ◽  
Author(s):  
Liangwei Dong ◽  
Yueli Hu

A novel low-voltage low-power CMOS voltage reference independent of temperature is presented in this design. After considering the combined effect of (1) a perfect suppression of the temperature dependence of mobility; (2) the compensation of the channel length modulation effect on the temperature coefficient, a temperature coefficient of 10 ppm/[Formula: see text]C is achieved. Moreover, by adopting the subthreshold MOSFETs, there are no resistors used in the proposed structure. Therefore, the maximum supply current measured at the maximum supply voltage is 70 nA and at 80[Formula: see text]C. The circuit can be used as a voltage reference for high performance and low power dissipation on a single chip.


2014 ◽  
Vol 1633 ◽  
pp. 95-100
Author(s):  
Forough Mahmoudabadi ◽  
Ta-Ko Chuang ◽  
Jerry Ho Kung ◽  
Miltiadis K. Hatalis

ABSTRACTIn this paper, we present fabrication and characterization of RF sputtered a-IGZO TFTs having a modified etch stopper structure with source/drain contact windows on glass wafers. The effect of annealing time and channel length on device performance in terms of mobility, on/off current ratio, average off current, threshold voltage, and sub threshold slope is reported.


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