Impact of interface layer and metal workfunction on device performance of ferroelectric junctionless cylindrical surrounding gate transistors

2017 ◽  
Vol 111 ◽  
pp. 194-205 ◽  
Author(s):  
Hema Mehta ◽  
Harsupreet Kaur
Keyword(s):  
Interface Layer ◽  
Device Performance ◽  
Surrounding Gate

Device performance of transistors with high-/spl kappa/ dielectrics using cross-wafer-scaled interface-layer thickness

2006 ◽  
Vol 27 (7) ◽  
pp. 546-548 ◽  
Author(s):  
B.J. O'Sullivan ◽  
V.S. Kaushik ◽  
L.-A. Ragnarsson ◽  
B. Onsia ◽  
N. Van Hoornick ◽  
...  
Keyword(s):  
Layer Thickness ◽  
Interface Layer ◽  
Device Performance

scholarly journals Impact of the interface layer on the cycling behaviour and retention of ferroelectric hafnium oxide

MRS Advances ◽  
2021 ◽  
Author(s):  
Maximilian Lederer ◽  
Konstantin Mertens ◽  
Alireza M. Kia ◽  
Jennifer Emara ◽  
Ricardo Olivo ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Interface Layer ◽  
Device Performance ◽  
Additional Insight ◽  
Central Aspect ◽  
Silicon Doped ◽  
The Impact ◽  
Ferroelectric Behaviour

Abstract Reliability is a central aspect of hafnium oxide-based ferroelectric field effect transistors (FeFETs), which are promising candidates for embedded non-volatile memories. Besides the device performance, understanding the evolution of the ferroelectric behaviour of hafnium oxide over its lifetime in FeFETs is of major importance for further improvements. Here, we present the impact of the interface layer in FeFETs on the cycling behaviour and retention of ferroelectric silicon-doped hafnium oxide. Thicker interfaces are demonstrated to reduce the presence of antiferroelectric-like wake-up effects and to improve endurance. However, they show a strong destabilisation of one polarisation state in terms of retention. In addition, measurements of the Preisach density revealed additional insight in the wake-up effect of these metal-ferroelectric-insulator-semiconductor (MFIS) capacitors. Graphic abstract

Impact of laterally asymmetric channel and gate stack architecture on device performance of surrounding gate MOSFETs

2010 ◽  
Vol 52 (3) ◽  
pp. 746-750
Author(s):  
Harsupreet Kaur ◽  
Sneha Kabra ◽  
Subhasis Haldar ◽  
R. S. Gupta
Keyword(s):  
Device Performance ◽  
Asymmetric Channel ◽  
Gate Stack ◽  
Surrounding Gate

An electrochemically deposited film as an interface layer to improve the performance of polymer light-emitting diodes

2014 ◽  
Vol 2 (21) ◽  
pp. 4117-4120 ◽  
Author(s):  
Tiancheng Yu ◽  
Xiaoyan Wu ◽  
Ying Lv ◽  
Linlin Liu ◽  
Luyang Du ◽  
...  
Keyword(s):  
Thin Film ◽  
Light Emitting Diodes ◽  
Interface Layer ◽  
Device Performance ◽  
Solution Processed ◽  
Light Emitting ◽  
Electrochemically Deposited ◽  
Polymer Light Emitting Diodes ◽  
Deposited Film

An insoluble electrochemically cross-linked thin film is successfully applied as an interface layer between PEDOT:PSS and the light emitting layer in solution-processed polymer light-emitting diodes for enhanced device performance.

Particle characterization of CVD tungsten metallization for 64 MBIT DRAM

1991 ◽  
Vol 49 ◽  
pp. 896-897
Author(s):  
Marylyn Bennett-Lilley ◽  
Thomas T.H. Fu ◽  
David D. Yin ◽  
R. Allen Bowling
Keyword(s):  
Chemical Vapor ◽  
Device Performance ◽  
Particle Characterization ◽  
Particle Generation ◽  
Tungsten Hexafluoride ◽  
Homogeneous Particle ◽  
Multiple Levels ◽  
Circuit Density ◽  
Sources Of Contamination

Chemical Vapor Deposition (CVD) tungsten metallization is used to increase VLSI device performance due to its low resistivity, and improved reliability over other metallization schemes. Because of its conformal nature as a blanket film, CVD-W has been adapted to multiple levels of metal which increases circuit density. It has been used to fabricate 16 MBIT DRAM technology in a manufacturing environment, and is the metallization for 64 MBIT DRAM technology currently under development. In this work, we investigate some sources of contamination. One possible source of contamination is impurities in the feed tungsten hexafluoride (WF6) gas. Another is particle generation from the various reactor components. Another generation source is homogeneous particle generation of particles from the WF6 gas itself. The purpose of this work is to investigate and analyze CVD-W process-generated particles, and establish a particle characterization methodology.

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

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