Fabrication of stable low voltage organic bistable memory device

2012 ◽  
Vol 161 (1) ◽  
pp. 684-688 ◽  
Author(s):  
CH.V.V. Ramana ◽  
M.K. Moodely ◽  
V. Kannan ◽  
A. Maity ◽  
J. Jayaramudu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Memory Device

Low-voltage electro-optical memory device based on NiO nanorods dispersed in a ferroelectric liquid crystal

RSC Advances ◽  
2016 ◽  
Vol 6 (59) ◽  
pp. 53873-53881 ◽  
Author(s):  
Achu Chandran ◽  
Jai Prakash ◽  
Jitendra Gangwar ◽  
Tilak Joshi ◽  
Avanish Kumar Srivastava ◽  
...  
Keyword(s):  
Liquid Crystal ◽  
Low Power ◽  
Nickel Oxide ◽  
Nonvolatile Memory ◽  
Low Voltage ◽  
Optical Memory ◽  
Memory Device ◽  
Ferroelectric Liquid Crystal ◽  
Oxide Nanorods ◽  
Nonvolatile Memory Device

A low-power nonvolatile memory device is fabricated by dispersing nickel oxide nanorods (nNiO) into a ferroelectric liquid crystal (FLC) host. The dipolar nNiO adsorbed ions in the FLC and thereby reduced the screening effect, which resulted in the enhanced memory behavior.

Investigation of Switching Phenomenon in Metal-Tantalum Oxide Interface

2015 ◽  
Vol 15 (10) ◽  
pp. 7564-7568 ◽  
Author(s):  
Abbas Yawar ◽  
Mi Ra Park ◽  
Quanli Hu ◽  
Woo Jin Song ◽  
Tae-Sik Yoon ◽  
...  
Keyword(s):  
Low Voltage ◽  
Tantalum Oxide ◽  
High Resistance State ◽  
Amorphous Layer ◽  
Memory Device ◽  
Ohmic Conduction ◽  
Oxide Interface ◽  
Bipolar Switching ◽  
Switching Phenomenon ◽  
Resistance State

To investigate the nature of the switching phenomenon at the metal-tantalum oxide interface, we fabricated a memory device in which a tantalum oxide amorphous layer acted as a switching medium. Different metals were deposited on top of the tantalum oxide layer to ensure that they will react with some of the oxygen contents already present in the amorphous layer of the tantalum oxide. This will cause the formation of metal oxide (MOx) at the interface. Two devices with Ti and Cu as the top electrodes were fabricated for this purpose. Both devices showed bipolar switching characteristics. The SET and RESET voltages for the Ti top electrode device were ∼+1.7 V and ∼−2 V, respectively, whereas the SET and RESET voltages for the Cu top electrode device were ∼+0.9 V and ∼−0.9 V, respectively. In the high-resistance state (HRS) conduction, the mechanisms involved in the devices with Ti and Cu top electrodes were space-charge limited conduction (SCLC) and ohmic, respectively. On the other hand, in the low-resistance state (LRS), the Ti top electrode device undergoes SCLC at a high voltage and ohmic conduction at a low voltage, and the Cu top electrode again undergoes ohmic conduction. From the consecutive sweep cycles, it was observed that the SET voltage gradually decreased with the sweeps for the Cu top electrode device, whereas for the Ti top electrode device, the set voltage did not vary with the sweeps.

Low Voltage Operation of High-κ HfO2/TiO2/Al2O3Single Quantum Well for Nanoscale Flash Memory Device Applications

2008 ◽  
Vol 47 (3) ◽  
pp. 1818-1821 ◽  
Author(s):  
Siddheswar Maikap ◽  
Ting-Yu Wang ◽  
Pei-Jer Tzeng ◽  
Heng-Yuan Lee ◽  
Cha-Hsin Lin ◽  
...  
Keyword(s):  
Quantum Well ◽  
Flash Memory ◽  
Low Voltage ◽  
Memory Device ◽  
Low Voltage Operation ◽  
Device Applications

Organic low voltage rewritable memory device based on PEDOT:PSS/f-MWCNTs thin film

2012 ◽  
Vol 13 (11) ◽  
pp. 2582-2588 ◽  
Author(s):  
José A. Ávila-Niño ◽  
Wagner S. Machado ◽  
Alan O. Sustaita ◽  
E. Segura-Cardenas ◽  
M. Reyes-Reyes ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Voltage ◽  
Memory Device

Effects of Metal Nanocrystals and Traps in Tunneling Rate Measurements in Metal Nanocrystal Based Carbon Nanotube Memory

2006 ◽  
Vol 963 ◽  
Author(s):  
Udayan Ganguly ◽  
Tuo-Hung Hou ◽  
Edwin Kan
Keyword(s):  
Carbon Nanotube ◽  
Electric Fields ◽  
Flash Memory ◽  
Low Voltage ◽  
Memory Device ◽  
Tunneling Rate ◽  
Direct Tunneling ◽  
High Electric Fields ◽  
Tunneling Behavior ◽  
Tunneling Rates

ABSTRACTThe metal nanocrystal (NC) based carbon nanotube (CNT) memory device has been probed with tunneling rate measurements. Firstly, tunneling behavior at two temperatures (300K and 10K) is reported here to demonstrate the distinct charge tunneling behavior for traps versus NCs and understand their relative contributions to program operations. Low temperature measurements show clear differentiation for two regimes of quantum transport. The FN tunneling regime exhibits strong bias dependence and dominates at high electric fields producing larger tunneling rates than the direct tunneling regime. In comparison to traps, the metal NCs repel potential contours and hence produce higher electric fields that enhance tunneling. The FN tunneling diminishes when the charging of the nanocrystal or traps decreases (relaxes) the electric field in the tunnel dielectric (TD) enough for the low field direct tunneling to dominate. The direct tunneling occurs at low fields, and is less sensitive to electric fields. The NCs demonstrate faster tunneling which can be ascribed to their large tunneling cross-section compared to traps. This is despite the relative proximity of traps to the channel in our structure. Secondly, the tunneling rates for two different TDs of similar EOT (under linear approximation) have been characterized and compared. They are a homogenous evaporated SiO2 and layered dielectric consisting of an evaporated SiO2 and ALD Al2O3 stack. While the evaporated SiO2 based TD demonstrates the distinct NC versus trap tunnel rate performance, the layered TD demonstrates stronger resistance to tunneling to the NCs. This result is consistent with the low tunneling rates demonstrated in Al2O3 elsewhere. Finally, the program performance of the NC-CNT memory device is evaluated as 0.5 V threshold voltage (VT) shift for a charging pulse of 9V and 100 μs. Combining with previous results, this indicates that NC-CNT memory is a promising candidate for low voltage, fast, multi-level cell (MLC) operation with sub-lithographic (self-assembled) features for sub 30 nm FLASH memory node. From the device physics perspective, these measurements may serve as the calibration and validation for advanced tunneling calculations and device modeling for promising nanoscale charge-based non-volatile memories.

Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire

2013 ◽  
Vol 103 (15) ◽  
pp. 153102 ◽  
Author(s):  
Ko-Hui Lee ◽  
Jung-Ruey Tsai ◽  
Ruey-Dar Chang ◽  
Horng-Chih Lin ◽  
Tiao-Yuan Huang
Keyword(s):  
Polycrystalline Silicon ◽  
High Speed ◽  
Low Voltage ◽  
Silicon Nanowire ◽  
Memory Device ◽  
Floating Gate ◽  
Floating Gate Memory
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