Electrostatic discharge (ESD) protection of N-type silicon controlled rectifier with P-type MOSFET pass structure for high voltage operating I/O application

2013 ◽  
Vol 53 (2) ◽  
pp. 205-207 ◽  
Author(s):  
Kil-Ho Kim ◽  
Yong-Jin Seo
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Type Silicon ◽  
Esd Protection ◽  
P Type

scholarly journals Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 445
Author(s):  
Hou ◽  
Du ◽  
Yang ◽  
Liu ◽  
Liu
Keyword(s):  
Electrostatic Discharge ◽  
Cmos Process ◽  
Silicon Area ◽  
Lateral Dimension ◽  
Esd Protection ◽  
Layout Area ◽  
Protection Capability ◽  
P Type ◽  
Area Efficient

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

Novel Symmetrical Dual-Directional SCR With p-Type Guard Ring for High-Voltage ESD Protection

2021 ◽  
pp. 1-4
Author(s):  
Feibo Du ◽  
Kuan-Chang Chang ◽  
Xinnan Lin ◽  
Fei Hou ◽  
Le Chen ◽  
...  
Keyword(s):  
High Voltage ◽  
Guard Ring ◽  
Esd Protection ◽  
P Type

ESD Robustness Designs for the HV Power DEMOS

2012 ◽  
Vol 271-272 ◽  
pp. 1286-1290
Author(s):  
Shen Li Chen ◽  
Chi Ling Chu
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Unit Area ◽  
The Other ◽  
Esd Protection ◽  
Protection Devices ◽  
Protection Circuits

Two kinds of efficient electrostatic discharge (ESD) protection circuits in lateral drain extended MOSFETs (DEMOSFETs) will be designed and investigated in this paper. One kind of these test samples is fabricated with an SCR structure, which has the lowest turned-on resistance when it is triggered by a high voltage of ESD event. The SCR circuit is the most efficient of all protection devices in terms of ESD performance per unit area. Furthermore, the other type of these DUTs is an SCR with RC-triggered structure, which will have a small trigger voltage (Vt1) under ESD event, and then it obtains a good ESD immunity level.

scholarly journals Improved LDMOS‐SCR for high‐voltage electrostatic discharge (ESD) protection applications

2020 ◽  
Vol 56 (13) ◽  
pp. 680-682
Author(s):  
Wenqiang Song ◽  
Fei Hou ◽  
Feibo Du ◽  
Jizhi Liu ◽  
Zhiwei Liu ◽  
...  
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Esd Protection

S/D LDD Junction Stain/Delineation by Electrochemical Displacement with Illumination

2008 ◽  
Author(s):  
Re-Long Chiu ◽  
Tammy Chen ◽  
Shannon Chen
Keyword(s):  
Light Source ◽  
High Voltage ◽  
Practical Method ◽  
H2so4 Solution ◽  
Short Channel ◽  
Type Silicon ◽  
Anode Electrode ◽  
P Type

Abstract This article describes the use of an optimized electrochemical delineation technique with illumination to clearly delineate the P-N junction on Si in short channel devices. In this process, the samples are exposed to a light source while in an aqueous CuSO4/HF/H2SO4 solution which induces a junction voltage between N- and P- type silicon. The N+/P+ dopant regions become the cathode/anode electrode plates. The treatment is simple and reproducible which makes it a practical method for identifying junction related problems at localized areas on a chip. Examples are provided to show the effectiveness of this technique in identifying (1) junction implant shift, (2) N+/P-well junction leak, (3) partially blocked NLDD implant, and (4) P+/N+ junction in high voltage device.

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

scholarly journals Determination of piezo-resistive coefficient π44 in p-type silicon by comparing simulation and measurement of pressure sensors

AIP Advances ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 085005
Author(s):  
Kevin Lauer ◽  
Geert Brokmann ◽  
Mario Bähr ◽  
Thomas Ortlepp
Keyword(s):  
Pressure Sensors ◽  
Type Silicon ◽  
P Type
Sign in / Sign up

Export Citation Format

Share Document