scholarly journals Improved LDMOS‐SCR for high‐voltage electrostatic discharge (ESD) protection applications

2020 ◽  
Vol 56 (13) ◽  
pp. 680-682
Author(s):  
Wenqiang Song ◽  
Fei Hou ◽  
Feibo Du ◽  
Jizhi Liu ◽  
Zhiwei Liu ◽  
...  
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Esd Protection

ESD Robustness Designs for the HV Power DEMOS

2012 ◽  
Vol 271-272 ◽  
pp. 1286-1290
Author(s):  
Shen Li Chen ◽  
Chi Ling Chu
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Unit Area ◽  
The Other ◽  
Esd Protection ◽  
Protection Devices ◽  
Protection Circuits

Two kinds of efficient electrostatic discharge (ESD) protection circuits in lateral drain extended MOSFETs (DEMOSFETs) will be designed and investigated in this paper. One kind of these test samples is fabricated with an SCR structure, which has the lowest turned-on resistance when it is triggered by a high voltage of ESD event. The SCR circuit is the most efficient of all protection devices in terms of ESD performance per unit area. Furthermore, the other type of these DUTs is an SCR with RC-triggered structure, which will have a small trigger voltage (Vt1) under ESD event, and then it obtains a good ESD immunity level.

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

ESD protection for high voltage LDMOS with sense FET

2002 ◽  
Author(s):  
Y.S. Choi ◽  
J.J. Kim ◽  
C.K. Jeon ◽  
M.H. Kim ◽  
S.L. Kim ◽  
...  
Keyword(s):  
High Voltage ◽  
Esd Protection

Damage analysis in smart-power technology electrostatic discharge (ESD) protection devices

1999 ◽  
Vol 39 (6-7) ◽  
pp. 1143-1148 ◽  
Author(s):  
D. Pogany ◽  
N. Seliger ◽  
M. Litzenberger ◽  
H. Gossner ◽  
M. Stecher ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Damage Analysis ◽  
Smart Power ◽  
Esd Protection ◽  
Protection Devices

Low-Density Fan-Out Heterogeneous Integration of MEMS Tunable Capacitor and RF SOI Switch

2019 ◽  
Vol 2019 (1) ◽  
pp. 000051-000055
Author(s):  
Rameen Hadizadeh ◽  
Anssi Laitinen ◽  
Niko Kuusniemi ◽  
Volker Blaschke ◽  
David Molinero ◽  
...  
Keyword(s):  
High Voltage ◽  
Microelectromechanical Systems ◽  
Performance Metrics ◽  
Circuit Board ◽  
Low Density ◽  
Rf Switch ◽  
Tunable Capacitor ◽  
Esd Protection ◽  
Mems Device ◽  
The Impact

Abstract Using Low-Density Fan-Out (LDFO) packaging technology, a radio frequency (RF) microelectromechanical systems (MEMS) tunable capacitor array composed of electrostatically actuated beams on 180nm high-voltage CMOS silicon was heterogeneously integrated with a single-pole four-terminal (SP4T) RF switch on 180nm CMOS silicon-on-insulator (SOI). The primary objective of this study was to determine the manufacturability of this System-in-Package (SiP) design, which is proven at time zero through survival of the MEMS device based on acceptable MEMS performance metrics. In addition, the RF SOI switch provides high-voltage electrostatic discharge (ESD) protection for the MEMS device. Capacitive MEMS structures are particularly sensitive to unpredictable electrostatic charging scenarios, such as handling after package assembly and printed circuit board (PCB) surface mount processing. Consequently, resistance to dielectric breakdown by means of robust ESD protection is a very desirable quality. Integrating the RF switch in close proximity with the MEMS device not only enables the ability to withstand charging scenarios in excess of 1kV (human body model), it mitigates the impact of parasitics on RF performance by minimizing interconnect lengths and complexity.

scholarly journals Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3340
Author(s):  
Shen-Li Chen ◽  
Yi-Cih Wu
Keyword(s):  
High Voltage ◽  
Field Effect Transistor ◽  
Electrostatic Discharge ◽  
Reference Sample ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Physical Parameters ◽  
Reliability Improvement ◽  
Drain Side ◽  
Effect Transistor

High-voltage n-channel lateral-diffused metal-oxide-semiconductor field-effect transistor (nLDMOS) components, fabricated by a TSMC 0.25-m 60-V bipolar-CMOS-DMOS (BCD) process with drain-side embedded silicon-controlled rectifier (SCR) of the n-p-n-arranged and p-n-p-arranged types, were investigated, in order to determine the devices’ electrostatic discharge (ESD)-sensing behavior and capability by discrete anode engineering. As for the drain-side n-p-n-arranged type with discrete-anode manners, transmission–line–pulse (TLP) testing results showed that the ESD ability (It2 value) was slightly upgraded. When the discrete physical parameter was 91 rows, the optimal It2 reached 2.157 A (increasing 17.7% compared with the reference sample). On the other hand, the drain-side SCR p-n-p-arranged type with discrete-anode manner had excellent SCR behavior, and its It2 values could be increased to >7 A (increasing >281.9% compared with the reference DUT). Moreover, under discrete anode engineering, the drain-side SCR n-p-n-arranged and p-n-p-arranged types had clearly higher ESD ability, except for the few discrete physical parameters. Therefore, using the anode discrete engineering, the ESD dissipation ability of a high-voltage (HV) nLDMOS with drain-side SCRs will have greater effectiveness.

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