Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

In this work, drain current ID for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. For this work, we used the non-equilibrium Green's function (NEGF) approach and self-consistent solution of Poisson's equation with Schrodinger's equation. The conduction band splitting into multiple sub-bands has been considered and there is no doping in channel in case of IM SiNT MOSFET. The effect of DM gate engineering for SiNT channel radius 1.5 nm with 0.8-nm gate oxide (SiO2) thickness on ID has been studied. A comparison of results has been done between IM DM DSG and JL DM DSG CGAA SiNT. In case of JL, doping concentration is optimized for two concerns: (i) to get the same IOn current as IM device and (ii) to get the same threshold voltage VTh as IM. This has resulted in 102 and 103 times smaller IOff in matching IOn and VTh optimized device, respectively, as compared to IM. It is found that DM gate engineering reduces drain-induced barrier lowering (DIBL) for both IM and JL SiNT MOSFET. In this work, JL have much smaller DIBL ~15 mV/V, almost an ideal SS ~60 mV/dec, and higher IOn/IOff ratio ~2.18·108 as compared to available CGAA literature results. Keywords: inversion mode, junctionless, DM DSG, Si nanotube MOSFET, NEGF, ID, SS, DIBL.

A Temperature-Dependent Threshold Voltage Model for SiGe Source/Drain Si–NT JLFET

In this paper, we investigate the impact of temperature on threshold voltage in the SiGe source/drain silicon-nanotube junctionless field effect transistor (NT JLFET). A threshold voltage model has been derived with inclusion of temperature for presented device. It is found that when the temperature increases from T = 300 K, T = 400 K, and T = 500 K, the strain produced by the SiGe source/drain on channel has been relaxed. However, the elevated temperature decreases the potential and the electric field in channel due to increases in intrinsic carrier concentration which further shifts the Fermi level towards the band gap. It has been evaluating that the threshold voltage roll-off and the short channel effects increases due to increases in temperature. The numerical results of threshold voltage model have been well compared with results of 2-D technology computer aided design (TCAD) simulations.