Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

2012 ◽  
Vol 52 (6) ◽  
pp. 1182-1188 ◽  
Author(s):  
Kyoung-Lim Suk ◽  
Kyosung Choo ◽  
Sung Jin Kim ◽  
Jong-Soo Kim ◽  
Kyung-Wook Paik
Keyword(s):  
Metal Layer ◽  
Printed Circuits ◽  
Fine Pitch ◽  
Chip On Film

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

2015 ◽  
Vol 2015 (1) ◽  
pp. 000379-000385 ◽  
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Additive Process ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch

2016 ◽  
Vol 13 (3) ◽  
pp. 128-135
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses ◽  
Low Permittivity

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates > 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Latest advancement of fully additive process for 8 µm ultra-fine pitch chip-on-film (COF) by nano-size Ni–P metallization

2018 ◽  
Vol 29 (8) ◽  
pp. 6937-6949 ◽  
Author(s):  
Kelvin P. L. Pun ◽  
Lafir Ali ◽  
Makoto Kohtoku ◽  
Chee-Wah Cheung ◽  
Alan H. S. Chan ◽  
...  
Keyword(s):  
Additive Process ◽  
Fine Pitch ◽  
Chip On Film ◽  
Nano Size

Chip-last Embedded Actives and Passives in Ultra-Miniaturized Organic Packages with Chip-First Benefits

2010 ◽  
Vol 2010 (1) ◽  
pp. 000537-000542
Author(s):  
Nitesh Kumbhat ◽  
Fuhan Liu ◽  
Venky Sundaram ◽  
Vivek Sridharan ◽  
Abhishek Choudhury ◽  
...  
Keyword(s):  
High Performance ◽  
Metal Layer ◽  
Stress Test ◽  
Heterogeneous Systems ◽  
Wafer Level ◽  
Fine Pitch ◽  
Low Profile ◽  
Organic Packages ◽  
Accelerated Stress Test ◽  
Reliability Performance

Embedded actives and passives are being pursued by chip-first and wafer-level fan-out approaches to address high functionality and miniaturization. A next generation embedding alternative- “chip-last embedding”, which retains all the benefits of chip-first, has been demonstrated at Georgia Tech for complex multi-component heterogeneous systems. This paper presents detailed results from the first demonstration of this novel technology called Embedded MEMS, Actives and Passives (EMAP) with Chip-Last (CL) interconnections. This technology is targeted at highly integrated modules and systems with multiple 2D and 3D ICs for RF, Digital, Analog, MEMS and passive devices. Ultra-thin (55μm) silicon test dies were embedded in a 60μm deep cavity within 6-metal layer substrates yielding a total module thickness of 0.22mm. The robustness of substrate materials and processes was demonstrated using thermal cycling of the blind-vias and through-holes. The embedded IC was bonded to the substrate at 160°C by ultra-fine pitch (30–50μm) and low-profile (10–15μm) Cu-to-Cu interconnections with polymer adhesives. Two different die-sizes 3mm × 3mm and 7mm × 7mm were investigated for reliability performance of these interconnections, which passed 1000 thermal cycles, in addition to Highly Accelerated Stress Test (HAST) and High Temperature Storage Test (HTS). Comprehensive analysis of new materials and processes used in the chip-last embedding technology has been carried out demonstrating the advantages and robustness of this promising technology. Due to manufacturing process simplicity and unparalleled set of benefits, the chip-last technology provides the benefits of chip-first while enabling highly miniaturized, multi-band, high performance modules with embedded actives and passives.

Thermodynamic Modeling of the Formation of Chromium Carbides in an Applied Metal Layer

2020 ◽  
Vol 40 (10) ◽  
pp. 843-847
Author(s):  
N. P. Aleshin ◽  
N. V. Kobernik ◽  
A. S. Pankratov ◽  
V. V. Petrova
Keyword(s):  
Thermodynamic Modeling ◽  
Metal Layer ◽  
Chromium Carbides
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