Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

2011 ◽  
Vol 51 (8) ◽  
pp. 1315-1324 ◽  
Author(s):  
Chun-Yu Lin ◽  
Li-Wei Chu ◽  
Ming-Dou Ker
Keyword(s):  
Rf Circuits ◽  
Cmos Process ◽  
60 Ghz ◽  
Design And Implementation ◽  
Esd Protection

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

2007 ◽  
Author(s):  
Yuan-Wen Hsiao ◽  
Ming-Dou Ker ◽  
Po-Yen Chiu ◽  
Chun Huang ◽  
Yuh-Kuang Tseng
Keyword(s):  
High Speed ◽  
Cmos Process ◽  
Esd Protection

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

60 GHz injection locked frequency quadrupler with quadrature outputs in 65 nm CMOS process

2009 ◽  
Author(s):  
Shoichi Hara ◽  
Takahiro Sato ◽  
Rui Murakami ◽  
Kenichi Okada ◽  
Akira Matsuzawa
Keyword(s):  
Cmos Process ◽  
60 Ghz

An Extended-Counting Incremental Sigma–Delta ADC with Hardware-Reuse Technique

2016 ◽  
Vol 25 (05) ◽  
pp. 1650038
Author(s):  
Xinji Zeng ◽  
Jing Gao ◽  
Liu Yang ◽  
Jiangtao Xu
Keyword(s):  
Conversion Rate ◽  
Cmos Process ◽  
Digital Output ◽  
Sigma Delta ◽  
Design And Implementation ◽  
Conversion Time ◽  
Cyclic Adc ◽  
Sigma Delta Adc ◽  
Oversampling Ratio ◽  
Least Significant Bits

This paper presents the design and implementation of an extended-counting incremental sigma–delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the “coarse phase” and the “fine phase”. In the “coarse phase”, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the “fine phase”, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5[Formula: see text][Formula: see text]m CMOS process, which has a conversion rate of 43.48[Formula: see text]kS/s with oversampling ratio (OSR) of 23 and achieves 84.83[Formula: see text]dB SNDR and 13.799-bit ENOB. It consumes 2.4[Formula: see text]mW with a 5[Formula: see text]V voltage supply, and the FOM is 3.87[Formula: see text]pJ/step.

scholarly journals High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 815 ◽  
Author(s):  
Seokha Hwang ◽  
Seungsik Moon ◽  
Dongyun Kam ◽  
Inn-Yeal Oh ◽  
Youngjoo Lee
Keyword(s):  
High Speed ◽  
Near Field ◽  
Rf Circuits ◽  
60 Ghz ◽  
Video Streams ◽  
Iterative Processing ◽  
Block Level ◽  
Quality Of Transmission ◽  
Processing Steps

This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

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