ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process

Chun-Yu Lin; Li-Wei Chu; Ming-Dou Ker

doi:10.1109/tmtt.2011.2178425

ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/tmtt.2011.2178425 ◽

2012 ◽

Vol 60 (3) ◽

pp. 714-723 ◽

Cited By ~ 15

Author(s):

Chun-Yu Lin ◽

Li-Wei Chu ◽

Ming-Dou Ker

Keyword(s):

Cmos Process ◽

60 Ghz ◽

Esd Protection

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Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

Microelectronics Reliability ◽

10.1016/j.microrel.2011.03.016 ◽

2011 ◽

Vol 51 (8) ◽

pp. 1315-1324 ◽

Cited By ~ 7

Author(s):

Chun-Yu Lin ◽

Li-Wei Chu ◽

Ming-Dou Ker

Keyword(s):

Rf Circuits ◽

Cmos Process ◽

60 Ghz ◽

Design And Implementation ◽

Esd Protection

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ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

2007 IEEE International SOC Conference ◽

10.1109/socc.2007.4545474 ◽

2007 ◽

Cited By ~ 1

Author(s):

Yuan-Wen Hsiao ◽

Ming-Dou Ker ◽

Po-Yen Chiu ◽

Chun Huang ◽

Yuh-Kuang Tseng

Keyword(s):

High Speed ◽

Cmos Process ◽

Esd Protection

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An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio

2008 IEEE Radio Frequency Integrated Circuits Symposium ◽

10.1109/rfic.2008.4561386 ◽

2008 ◽

Cited By ~ 37

Author(s):

Emanuel Cohen ◽

Shmuel Ravid ◽

Dan Ritter

Keyword(s):

Low Power ◽

Cmos Process ◽

Phase Array ◽

60 Ghz ◽

Ultra Low Power

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Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2003.812495 ◽

2003 ◽

Vol 50 (4) ◽

pp. 1050-1057 ◽

Cited By ~ 15

Author(s):

Ming-Dou Ker ◽

Tung-Yang Chen

Keyword(s):

Cmos Process ◽

Esd Protection ◽

On Chip

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60 GHz injection locked frequency quadrupler with quadrature outputs in 65 nm CMOS process

2009 Asia Pacific Microwave Conference ◽

10.1109/apmc.2009.5385434 ◽

2009 ◽

Cited By ~ 4

Author(s):

Shoichi Hara ◽

Takahiro Sato ◽

Rui Murakami ◽

Kenichi Okada ◽

Akira Matsuzawa

Keyword(s):

Cmos Process ◽

60 Ghz

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A 28- and 60-GHz Dual-Band On-Chip Antenna for 5G-Compatible IoT-Served Sensors in Standard CMOS Process

IEEE Transactions on Antennas and Propagation ◽

10.1109/tap.2020.3025236 ◽

2020 ◽

pp. 1-1

Author(s):

Pascal Burasa ◽

Tarek Djerafi ◽

Ke Wu

Keyword(s):

Dual Band ◽

Cmos Process ◽

60 Ghz ◽

Standard Cmos Process ◽

On Chip Antenna ◽

On Chip

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MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.3.429 ◽

2005 ◽

Vol E88-C (3) ◽

pp. 429-436 ◽

Cited By ~ 1

Author(s):

M.-D. KER

Keyword(s):

Deep Submicron ◽

Cmos Process ◽

Esd Protection ◽

Submicron Cmos ◽

On Chip

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Efficient 60-GHz Power Amplifier With Adaptive AM-AM and AM-PM Distortions Compensation in 65-nm CMOS Process

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/tmtt.2020.2985953 ◽

2020 ◽

Vol 68 (7) ◽

pp. 3045-3055

Author(s):

Kyung Pil Jung ◽

Hyuk Su Son ◽

Joon Hyung Kim ◽

Chul Soon Park

Keyword(s):

Power Amplifier ◽

Cmos Process ◽

60 Ghz

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Optimization of LDMOS-SCR Device For ESD Protection Based On 0.5 μm CMOS Process

2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo) ◽

10.1109/emccompo.2019.8919854 ◽

2019 ◽

Author(s):

Xiangliang Jin ◽

Yang Wang ◽

Zeyu Zhong

Keyword(s):

Cmos Process ◽

Esd Protection

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ESD protection design for wideband RF applications in 65-nm CMOS process

2014 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2014.6865426 ◽

2014 ◽

Cited By ~ 1

Author(s):

Li-Wei Chu ◽

Chun-Yu Lin ◽

Ming-Dou Ker ◽

Ming-Hsiang Song ◽

Jen-Chou Tseng ◽

...

Keyword(s):

Cmos Process ◽

Esd Protection ◽

Rf Applications

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