NIR laser stimulation for dynamic timing analysis

2005 ◽  
Vol 45 (9-11) ◽  
pp. 1459-1464 ◽  
Author(s):  
K. Sanchez ◽  
R. Desplats ◽  
F. Beaudoin ◽  
P. Perdu ◽  
J.P. Roux ◽  
...  
2018 ◽  
Vol 29 (35) ◽  
pp. 355704 ◽  
Author(s):  
Zhaojing Ba ◽  
Min Hu ◽  
Yiming Zhao ◽  
Yiqing Wang ◽  
Jing Wang ◽  
...  

2011 ◽  
Vol 30 (2) ◽  
pp. 27-31
Author(s):  
V. Ponomarchuk ◽  
◽  
N. Khramenko ◽  
O. Guzun ◽  
Barudi Abdul Moneim ◽  
...  

Author(s):  
Magdalena Sienkiewicz ◽  
Philippe Rousseille

Abstract This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.


2018 ◽  
Author(s):  
Chun Haur Khoo

Abstract Driven by the cost reduction and miniaturization, Wafer Level Chip Scale Packaging (WLCSP) has experienced significant growth mainly driven by mobile consumer products. Depending on the customers or manufacturing needs, the bare silicon backside of the WLCSP may be covered with a backside laminate layer. In the failure analysis lab, in order to perform the die level backside fault isolation technique using Photon Emission Microscope (PEM) or Laser Signal Injection Microscope (LSIM), the backside laminate layer needs to be removed. Most of the time, this is done using the mechanical polishing method. This paper outlines the backside laminate removal method of WLCSP using a near infrared (NIR) laser that produces laser energy in the 1,064 nm range. This method significantly reduces the sample preparation time and also reduces the risk of mechanical damage as there is no application of mechanical force. This is an effective method for WLCSP mounted on a PCB board.


Author(s):  
Dominique Carisetti ◽  
Nicolas Sarazin ◽  
Nathalie Labat ◽  
Nathalie Malbert ◽  
Arnaud Curutchet ◽  
...  

Abstract To improve the long-term stability of AlGaN/GaN HEMTs, the reduction of gate and drain leakage currents and electrical anomalies at pinch-off is required. As electron transport in these devices is both coupled with traps or surface states interactions and with polarization effects, the identification and localization of the preeminent leakage path is still challenging. This paper demonstrates that thermal laser stimulation (TLS) analysis (OBIRCh, TIVA, XIVA) performed on the die surface are efficient to localize leakage paths in GaN based HEMTs. The first part details specific parameters, such as laser scan speed, scan direction, wavelength, and laser power applied for leakage gate current paths identification. It compares results obtained with Visible_NIR electroluminescence analysis with the ones obtained by the TLS techniques on GaN HEMT structures. The second part describes some failure analysis case studies of AlGaN/GaN HEMT with field plate structure which were successful, thanks to the OBIRCh technique.


Author(s):  
Chunlei Wu ◽  
Suying Yao

Abstract Lock-in IR-OBIRCH analysis, as a kind of static thermal laser stimulation (S-TLS) technique, is very effective to isolate a fault for the parametric failure cases. However, its capability is limited to localize a defect when the IC is operated under a defined operating condition. Whereas the dynamic thermal laser stimulation (D-TLS) technique is good at locating a fault while the IC is operated under some functions to activate the failure. In this paper, a novel method is presented to realize DTLS just by Lock-in IR-OBIRCH assisted with a Current Detection Probe Head. Two cases are studied to demonstrate the effectiveness of this method.


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