Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology

2011 ◽  
Vol 35 (4) ◽  
pp. 371-381 ◽  
Author(s):  
Hongbin Sun ◽  
Pengju Ren ◽  
Nanning Zheng ◽  
Tong Zhang ◽  
Tao Li
Keyword(s):  
Energy Efficient ◽  
High Performance ◽  
Soft Error ◽  
3D Integration ◽  
Error Resilient ◽  
Integration Technology

The European 3D Technology Platform (e-CUBES)

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000446-000501 ◽  
Author(s):  
Peter Ramm ◽  
Armin Klumpp ◽  
Josef Weber ◽  
Thomas Fritzsch ◽  
Maaike Taklo ◽  
...  
Keyword(s):  
System Integration ◽  
High Performance ◽  
Technological Development ◽  
Low Cost ◽  
Market Potential ◽  
3D Integration ◽  
3D Technology ◽  
Critical Dimensions ◽  
Technology Platform ◽  
Integration Technology

The European 3D technology platform that has been established represents the ensemble of 3D integration technologies which were developed within the e-CUBES project [http://www.ecubes.org]. It became evident that the fabrication of e-CUBES with their need for high-level miniaturization can only be realized by system integration technologies which use the third dimension. The main objective is to provide 3D integration technologies which on the one hand increase the performance sufficiently and at the same time allow for low cost fabrication in order to achieve products with a large market potential. The work was focussed on the requirements coming from application demonstrators. However, other requirements set by taking the visionary approach of developing strongly miniaturized micro/nano-systems were also a major task of the work. Research and technological development was necessary in the following fields in order to achieve the objectives. Seven corresponding technologies were successfully developed building a European platform on 3D Integration. This is considered to be essential output of the e-CUBES project. These are in the 3D integration categoriesVertical System Integration (3D-SOC): Fraunhofer IZM-M's Through-Si Via (TSV) Technology (ICV-SLID) and SINTEF's Hollow Via & Gold Stud Bump Bonding (HoViGo),Chip Stacking (3D-WLP): IMEC / Fraunhofer IZM's Thin-Chip-Integration Technology (TCI/UTCS) and CEA-LETI's Via Belt Technology, and3D Assembly (3D-SIP): 3D-PLUS' High Performance Package-in-Package (HiPPiP) and Wireless Die-on-Die (WDoD) Technologies, as well as Tyndall's Submicron Wire Anisotropic Conductive Film Technology (SW-ACF). Four optimized 3D integration technologies were successfully used in the development of three e-CUBES application demonstrators: Thin-Chip-Integration technology (TCI/UTCS) for Philips' Health & Fitness demonstrator, TSV technology ICV-SLID and HoViGo for Infineon's Automotive demonstrator (TPMS) and Package-in-Package technology HiPPiP for Thales' Aeronautic demonstrator. The 3D integration technologies which form part of the established e-CUBES platform will be presented including key characteristics, critical dimensions, electrical parameters and adaptability to new applications.

Challenges And Energy Efficient Techniques For High Performance Wireless Communications

2015 ◽  
Vol 1 (4) ◽  
pp. 1-12
Author(s):  
Chidadala Janardhan ◽  
◽  
Bhagath Pyda ◽  
J. Manohar ◽  
K. V. Ramanaiah ◽  
...  
Keyword(s):  
Wireless Communications ◽  
Energy Efficient ◽  
High Performance

scholarly journals Thread Batching for High-performance Energy-efficient GPU Memory Design

2019 ◽  
Vol 15 (4) ◽  
pp. 1-21
Author(s):  
Bing Li ◽  
Mengjie Mao ◽  
Xiaoxiao Liu ◽  
Tao Liu ◽  
Zihao Liu ◽  
...  
Keyword(s):  
Energy Efficient ◽  
High Performance ◽  
Memory Design
Sign in / Sign up

Export Citation Format

Share Document