Fabrication on uniform plating-based flip chip solder bumps after reflow process using a polishing mechanism

2007 ◽  
Vol 84 (1) ◽  
pp. 60-71 ◽  
Author(s):  
Pen-Shan Chao ◽  
Jung-Tang Huang ◽  
Hou-Jun Hsu ◽  
Sheng-Hsiung Shih
Keyword(s):  
Flip Chip ◽  
Reflow Process ◽  
Solder Bumps

Large-Scale Model of Flip-Chip Joining Defects

2014 ◽  
Author(s):  
Julien Sylvestre ◽  
Maud Samson ◽  
Éric Duchesne ◽  
Dominique Langlois-Demers
Keyword(s):  
Large Scale ◽  
Flip Chip ◽  
Energy Scale ◽  
Scale Model ◽  
Volume Distribution ◽  
Reflow Process ◽  
Solder Bumps ◽  
Large Scale Model ◽  
Solder Volume ◽  
Data Reduction Technique

A numerical model is developed for the flip chip reflow process, including many significant aspects of the joining dynamics: thermal expansion of the device and substrate; temperature-dependent substrate warpage; random variations of the solder volume with position; and global device position above the substrate. A detailed micro-model of each interconnect captures the transition from two contacting solder bumps to a single continuous solder interconnect, using a random wetting delay parameterized by the surface energy of the bumps relative to an energy scale. The model is shown to correctly fit measurements of the device position during the reflow process, and is used to study the occurrence of non-wet and bridge defects. The effects of spatial variations in the solder volume distribution on these defects is studied in details for an actual device with 12 504 interconnections, using an effective data reduction technique.

Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps

2005 ◽  
Vol 127 (4) ◽  
pp. 440-445 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Heat Flux ◽  
Flip Chip ◽  
Flow Direction ◽  
Void Formation ◽  
Reflow Process ◽  
Solidification Direction ◽  
Solder Bumps ◽  
Test Board ◽  
Bottom To Top ◽  
High Lead

Experiments were carried out to investigate the effect of reversing the heat flux direction during cooling on the formation of voids during the reflow process. Under different upward and downward solidification conditions, 480 high-lead (90Pb∕8Sn∕2Ag) solder joints of flip-chip assemblies were processed. The solder samples were then microsectioned to determine the size and location of voids. The results show that reversing the flow direction during cooling has a significant effect on the final void formation. For the case of the melting direction from top (flip-chip side) to bottom (test board side), reversing the heat flux direction results in solidification direction from top to bottom. The percentage of defective bumps was found to be 28% and the volume of voids per defective bump was 1.5%. This is the best reflow methodology to minimize voids. Without reversing the heat flux the defective bumps were 80% with 4.0% void volume. In the case of solidification direction/melting direction from bottom to top, the percentage of defective bumps increases from 40% to 51%, accompanying a rise of the volume of voids from 3.0% to 3.7%.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

A Fluxless Flip-Chip Bonding for VCSEL Arrays Using Silver-Coated Indium Solder Bumps

2004 ◽  
Vol 27 (4) ◽  
pp. 246-253 ◽  
Author(s):  
K.-M. Chu ◽  
J.-S. Lee ◽  
H.S. Cho ◽  
H.-H. Park ◽  
D.Y. Jeon
Keyword(s):  
Flip Chip ◽  
Flip Chip Bonding ◽  
Solder Bumps ◽  
Vcsel Arrays
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