Effect of High Temperature Storage on Reliability of Sn-Ag-Cu Flip Chip Solder Bumps

2006 ◽  
Author(s):  
Xingjia Huang ◽  
S.W. Ricky Lee ◽  
Ming Li ◽  
William T. Chen
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Solder Bumps ◽  
High Temperature Storage ◽  
Temperature Storage

scholarly journals FCCSP IMC growth under reliability stress follows automotive criteria

2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
Temperature Cycling ◽  
Content Type ◽  
Initial Stage ◽  
High Temperature Storage ◽  
Temperature Cycling Test ◽  
Temperature Storage

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

Active and Passive Devices Embedded in Laminate-Based Multilayer Board

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao
Keyword(s):  
High Temperature ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Wafer Level ◽  
Active Device ◽  
Electrical Connection ◽  
Passive Devices ◽  
High Temperature Storage ◽  
Circuit Resistance ◽  
Temperature Storage

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.

Stability of Flip-Chip Interconnects Assembled with Al/Ni(V)/Cu-UBM and Eutectic Pb-Sn Solder During Exposure to High-Temperature Storage

2008 ◽  
Vol 38 (2) ◽  
pp. 303-324 ◽  
Author(s):  
J. Osenbach ◽  
A. Amin ◽  
M. Bachman ◽  
F. Baiocchi ◽  
D. Bitting ◽  
...  
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
High Temperature Storage ◽  
Temperature Storage

scholarly journals A Study of the Intermetallic Compound Growth in Flip-Chip Packages under Thermal Loading

2019 ◽  
Vol 8 (1) ◽  
pp. 1-7
Author(s):  
C. Xu ◽  
Z.W. Zhong ◽  
W.K. Choi
Keyword(s):  
Intermetallic Compound ◽  
Flip Chip ◽  
Thermal Loading ◽  
Good Condition ◽  
Nickel Layer ◽  
Intermetallic Compound Growth ◽  
Solder Bumps ◽  
High Temperature Storage ◽  
Before And After ◽  
Temperature Storage

 The intermetallic compound layers in solder bumps have the brittle feature and can easily fracture under thermal or mechanical loading. Therefore, the intermetallic compound is an issue for the fracture reliability of the solder bumps. In this work, the intermetallic compound growth before and after high temperature storage tests was investigated. The experiment results revealed that the solder bumps with nickel layers could reduce the intermetallic compound growth rate. The nickel layer, which was added in between Cu and SnAg for top solder bumps, was an important factor controlling the intermetallic compound thickness. It was hard to tell the intermetallic compound thickness at time zero; at the time of 147 hours, the intermetallic compound grew to 3.25 µm; at the time of 294 hours, the intermetallic compound grew to 5.25 µm. However, the solder joints were still in good condition.

scholarly journals Experimental and Theoretical Studies of Cu-Sn Intermetallic Phase Growth During High-Temperature Storage of Eutectic SnAg Interconnects

2020 ◽  
Vol 49 (12) ◽  
pp. 7194-7210
Author(s):  
A. Morozov ◽  
A. B. Freidin ◽  
V. A. Klinkov ◽  
A. V. Semencha ◽  
W. H. Müller ◽  
...  
Keyword(s):  
High Temperature ◽  
Chemical Reactions ◽  
Intermetallic Phase ◽  
Solder Bumps ◽  
High Temperature Storage ◽  
Theoretical Predictions ◽  
Reaction Constant ◽  
Experimental Findings ◽  
Microelectronic Components ◽  
Temperature Storage

AbstractIn this paper, the growth of intermetallic compound (IMC) layers is considered. After soldering, an IMC layer appears and establishes a mechanical contact between eutectic tin-silver solder bumps and Cu interconnects in microelectronic components. Intermetallics are relatively brittle in comparison with copper and tin. In addition, IMC formation is typically based on multi-component diffusion, which may include vacancy migration leading to Kirkendall voiding. Consequently, the rate of IMC growth has a strong implication on solder joint reliability. Experiments show that the intermetallic layers grow considerably when the structure is exposed to heat. Mechanical stresses may also affect intermetallic growth behavior. These stresses arise not only from external loadings but also from thermal mismatch of the materials constituting the joint, and from the mismatch produced by the change in shape and volume due to the chemical reactions of IMC formation. This explains why in this paper special attention is being paid to the influence of stresses on the kinetics of the IMC growth. We develop an approach that couples mechanics with the chemical reactions leading to the formation of IMC, based on the thermodynamically sound concept of the chemical affinity tensor, which was recently used in general statements and solutions of mechanochemistry problems. We start with a report of experimental findings regarding the IMC growth at the interface between copper pads and tin based solder alloys in different microchips during a high temperature storage test. Then we analyze the growth kinetics by means of a continuum model. By combining experiment, theory, and a comparison of experimental data and theoretical predictions we finally find the values of the diffusion coefficient and an estimate for the chemical reaction constant. A comparison with literature data is also performed.

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