Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps

2005 ◽  
Vol 127 (4) ◽  
pp. 440-445 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Heat Flux ◽  
Flip Chip ◽  
Flow Direction ◽  
Void Formation ◽  
Reflow Process ◽  
Solidification Direction ◽  
Solder Bumps ◽  
Test Board ◽  
Bottom To Top ◽  
High Lead

Experiments were carried out to investigate the effect of reversing the heat flux direction during cooling on the formation of voids during the reflow process. Under different upward and downward solidification conditions, 480 high-lead (90Pb∕8Sn∕2Ag) solder joints of flip-chip assemblies were processed. The solder samples were then microsectioned to determine the size and location of voids. The results show that reversing the flow direction during cooling has a significant effect on the final void formation. For the case of the melting direction from top (flip-chip side) to bottom (test board side), reversing the heat flux direction results in solidification direction from top to bottom. The percentage of defective bumps was found to be 28% and the volume of voids per defective bump was 1.5%. This is the best reflow methodology to minimize voids. Without reversing the heat flux the defective bumps were 80% with 4.0% void volume. In the case of solidification direction/melting direction from bottom to top, the percentage of defective bumps increases from 40% to 51%, accompanying a rise of the volume of voids from 3.0% to 3.7%.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Experiments on Fluid Mechanics in Flip-Chip Solder Connections

2003 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Flip Chip ◽  
Experimental Finding ◽  
Numerical Study ◽  
Void Formation ◽  
Molten Solder ◽  
Bottom Edge ◽  
Solder Bumps ◽  
Solder Reflow ◽  
Heating Profiles ◽  
Bottom To Top

This experimental research studies the formation of void bubbles within molten solder bumps in flip-chip connections. A theory based on thermocapillary flow reveals that the direction of heating influences void formation. Twelve chip-bump substrate assemblies were investigated using different heating profiles. A database on sizes and locations of voids in solder bumps was constructed. The observation on cases with melting direction from bottom to top supports the numerical study based on thermocapillary theory. The results show that a single big void is near the bump center with a few small voids near the edge when the melting direction is from bottom to top during solder reflow. When the melting direction was reversed, many small voids appear near the bottom edge with big voids in the middle of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory. However, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies

2004 ◽  
Vol 127 (2) ◽  
pp. 120-126 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Numerical Study ◽  
Void Formation ◽  
Middle Layer ◽  
Molten Solder ◽  
Previous Theory ◽  
Solder Interconnects ◽  
Heating Profiles ◽  
High Lead

Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. This paper reports experimental research on the formation of void bubbles within molten solder bumps in flip-chip connections. For flip-chip-soldered electronic components, which have small solder volume, voids can be more detrimental to reliability. A previous theory based on thermocapillary flow reveals that the direction of heating influences void formation. Using different heating profiles, 480 solder joints of flip-chip assemblies were processed. A high-lead 90Pb∕8Sn∕2Ag solder was employed in the experiments. The solder samples were microsectioned to determine the actual size or diameter of the voids. A database on sizes and locations of voids was then constructed. More defective bumps, 80%, and higher void volume were found when the solder was melted from top (flip-chip side) to bottom (test board side). The observation on cases with melting direction from bottom to top had 40% defective bumps. The results show that a single big void is near the solder bump center with a few small voids near the edge. This supports the numerical study based on the thermocapillary theory. When the melting direction was reversed, many small voids appear near the edge. Big and middle-size voids tend to stay in the middle and outer regions from top towards middle layer of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory, however, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Large-Scale Model of Flip-Chip Joining Defects

2014 ◽  
Author(s):  
Julien Sylvestre ◽  
Maud Samson ◽  
Éric Duchesne ◽  
Dominique Langlois-Demers
Keyword(s):  
Large Scale ◽  
Flip Chip ◽  
Energy Scale ◽  
Scale Model ◽  
Volume Distribution ◽  
Reflow Process ◽  
Solder Bumps ◽  
Large Scale Model ◽  
Solder Volume ◽  
Data Reduction Technique

A numerical model is developed for the flip chip reflow process, including many significant aspects of the joining dynamics: thermal expansion of the device and substrate; temperature-dependent substrate warpage; random variations of the solder volume with position; and global device position above the substrate. A detailed micro-model of each interconnect captures the transition from two contacting solder bumps to a single continuous solder interconnect, using a random wetting delay parameterized by the surface energy of the bumps relative to an energy scale. The model is shown to correctly fit measurements of the device position during the reflow process, and is used to study the occurrence of non-wet and bridge defects. The effects of spatial variations in the solder volume distribution on these defects is studied in details for an actual device with 12 504 interconnections, using an effective data reduction technique.

Fabrication on uniform plating-based flip chip solder bumps after reflow process using a polishing mechanism

2007 ◽  
Vol 84 (1) ◽  
pp. 60-71 ◽  
Author(s):  
Pen-Shan Chao ◽  
Jung-Tang Huang ◽  
Hou-Jun Hsu ◽  
Sheng-Hsiung Shih
Keyword(s):  
Flip Chip ◽  
Reflow Process ◽  
Solder Bumps

Measurement of electromigration activation energy in eutectic SnPb and SnAg flip-chip solder joints with Cu and Ni under-bump metallization

2010 ◽  
Vol 25 (9) ◽  
pp. 1847-1853 ◽  
Author(s):  
Hsiao-Yun Chen ◽  
Chih Chen
Keyword(s):  
Activation Energy ◽  
Flip Chip ◽  
Void Formation ◽  
Under Bump Metallization ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Snag Solder ◽  
Temperature Coefficient Of Resistivity ◽  
Eutectic Snpb ◽  
Real Temperature

Electromigration activation energy is measured by a built-in sensor that detects the real temperature during current stressing. Activation energy can be accurately determined by calibrating the temperature using the temperature coefficient of resistivity of an Al trace. The activation energies for eutectic SnAg and SnPb solder bumps are measured on Cu under-bump metallization (UBM) as 1.06 and 0.87 eV, respectively. The activation energy mainly depends on the formation of Cu–Sn intermetallic compounds. On the other hand, the activation energy for eutectic SnAg solder bumps with Cu–Ni UBM is measured as 0.84 eV, which is mainly related to void formation in the solder.

Damages and Microstructural Variation of High-lead and Eutectic SnPb Composite Flip Chip Solder Bumps Induced by Electromigration

2005 ◽  
Vol 20 (8) ◽  
pp. 2184-2193 ◽  
Author(s):  
Yeh-Hsiu Liu ◽  
Kwang-Lung Lin
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Electron Flow ◽  
Electron Probe Microanalyzer ◽  
Current Stressing ◽  
Solder Bumps ◽  
Underbump Metallization ◽  
Current Polarity ◽  
High Lead ◽  
Eutectic Snpb

The electromigration behavior of the high-lead and eutectic SnPb composite solder bumps was investigated at 150 °C with 5 × 103 A/cm2 current stressing for up to 1711 h. The diameter of the bumps was about 125 μm. The underbump metallization (UBM) on the chip side was sputtered Al/Ni(V)/Cu thin films, and the Cu pad on the board side was plated with electroless Ni/Au. It was observed that damages occurred in the joints in a downward electron flow (from chip side to the substrate side), while those joints having the opposite current polarity showed only minor changes. In the case of downward electron flow, electromigration damages were observed in the UBM and solder bumps. The vanadium in Ni(V) layer was broken under current stressing of 1711 h while it was still intact after current stressing of 1000 h. The electron probe microanalyzer (EPMA) elemental mapping clearly shows that the Al atoms in the trace migrated through the UBM into the solder bump during current stressing. Voids were found in the solder bump near the UBM/solder interface. The Sn-rich phases of the solder bumps showed gradual streaking and reorientation upon current stressing. This resulted in the formation of uniaxial Sn-rich phases in the middle of the solder bump, while the columnar and fibrous Sn-rich phases were formed in the surrounding regions. The formation mechanism of electromigration-induced damage to the UBM structure and solder bump were discussed.

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