MOCVD grown CdZn Te/GaAs/Si substrates for large-area HgCdTe IRFPAs

1993 ◽  
Vol 22 (8) ◽  
pp. 835-842 ◽  
Author(s):  
S. M. Johnson ◽  
J. A. Vigil ◽  
J. B. James ◽  
C. A. Cockrum ◽  
W. H. Konkel ◽  
...  
Keyword(s):  
Large Area ◽  
Si Substrates

Current Transport Mechanisms in Au-Free Metallizations for CMOS Compatible GaN HEMT Technology

2020 ◽  
Vol 1004 ◽  
pp. 725-730
Author(s):  
Fabrizio Roccaforte ◽  
Monia Spera ◽  
Salvatore Di Franco ◽  
Raffaella Lo Nigro ◽  
Patrick Fiorenza ◽  
...  
Keyword(s):  
Barrier Height ◽  
Ohmic Contacts ◽  
Specific Contact Resistance ◽  
Current Transport ◽  
Large Area ◽  
Si Substrates ◽  
Ohmic Behavior ◽  
Specific Contact ◽  
Thermionic Field Emission

Gallium nitride (GaN) and its AlGaN/GaN heterostructures grown on large area Si substrates are promising systems to fabricate power devices inside the existing Si CMOS lines. For this purpose, however, Au-free metallizations are required to avoid cross contaminations. In this paper, the mechanisms of current transport in Au-free metallization on AlGaN/GaN heterostructures are studied, with a focus on non-recessed Ti/Al/Ti Ohmic contacts. In particular, an Ohmic behavior of Ti/Al/Ti stacks was observed after an annealing at moderate temperature (600°C). The values of the specific contact resistance ρc decreased from 1.6×104 Ω.cm2 to 7×105 Ω.cm2 with increasing the annealing time from 60 to 180s. The temperature dependence of ρc indicated that the current flow is ruled by a thermionic field emission (TFE) mechanism, with barrier height values of 0.58 eV and 0.52 eV, respectively. Finally, preliminary results on the forward and reverse bias characterization of Au-free tungsten carbide (WC) Schottky contacts are presented. This contact exhibited a barrier height value of 0.82 eV.

Growth and processing of heteroepitaxial 3C-SiC films for electronic devices applications

2012 ◽  
Vol 1433 ◽  
Author(s):  
A. Severino ◽  
M. Mauceri ◽  
R. Anzalone ◽  
A. Canino ◽  
N. Piluso ◽  
...  
Keyword(s):  
Growth Parameters ◽  
Low Cost ◽  
Electronic Devices ◽  
Young Modulus ◽  
Interesting Property ◽  
Large Area ◽  
Si Substrates ◽  
Application Fields ◽  
Sic Films

ABSTRACT3C-SiC is very attractive due the chance to be grown on large-area, low-cost Si substrates. Moreover, 3C-SiC has higher channel electron mobility with respect to 4H-SiC, interesting property in MOSFET applications. Other application fields where 3C-SiC can play a significant role are solar cells and MEMS-based sensors. In this work, we present a general overview of 3C-SiC growth on Si substrate. The influence of growth parameters, such as the growth rate, on the crystal quality of 3C-SiC films is discussed. The main issue for 3C-SiC development is the reduction of the stacking fault density, which shows an exponential decreasing trend with the film thickness tending to a saturation value of about 1000 cm-1. Some aspect of processing will be also faced with the realization of cantilever for Young modulus calculations and the implantation of Al ions for the study of damaging and recovery of the 3C-SiC crystal.

MBE growth and device processing of MWIR HgCdTe on large area Si substrates

2001 ◽  
Vol 30 (6) ◽  
pp. 717-722 ◽  
Author(s):  
G. Brill ◽  
S. Velicu ◽  
P. Boieriu ◽  
Y. Chen ◽  
N. K. Dhar ◽  
...  
Keyword(s):  
Large Area ◽  
Mbe Growth ◽  
Si Substrates ◽  
Device Processing

scholarly journals Facile and Controllable Synthesis of Large-Area Monolayer WS2 Flakes Based on WO3 Precursor Drop-Casted Substrates by Chemical Vapor Deposition

Nanomaterials ◽  
2019 ◽  
Vol 9 (4) ◽  
pp. 578 ◽  
Author(s):  
Biao Shi ◽  
Daming Zhou ◽  
Shaoxi Fang ◽  
Khouloud Djebbi ◽  
Shuanglong Feng ◽  
...  
Keyword(s):  
Energy Gap ◽  
Growth Parameters ◽  
Fluorescence Emission ◽  
Chemical Vapor ◽  
Optical Microscope ◽  
Edge Length ◽  
Controllable Synthesis ◽  
Large Area ◽  
Si Substrates ◽  
Potential Applications

Monolayer WS2 (Tungsten Disulfide) with a direct-energy gap and excellent photoluminescence quantum yield at room temperature shows potential applications in optoelectronics. However, controllable synthesis of large-area monolayer WS2 is still challenging because of the difficulty in controlling the interrelated growth parameters. Herein, we report a facile and controllable method for synthesis of large-area monolayer WS2 flakes by direct sulfurization of powdered WO3 (Tungsten Trioxide) drop-casted on SiO2/Si substrates in a one-end sealed quartz tube. The samples were thoroughly characterized by an optical microscope, atomic force microscope, transmission electron microscope, fluorescence microscope, photoluminescence spectrometer, and Raman spectrometer. The obtained results indicate that large triangular monolayer WS2 flakes with an edge length up to 250 to 370 μm and homogeneous crystallinity were readily synthesized within 5 min of growth. We demonstrate that the as-grown monolayer WS2 flakes show distinctly size-dependent fluorescence emission, which is mainly attributed to the heterogeneous release of intrinsic tensile strain after growth.

scholarly journals Camphor-Based CVD Bilayer Graphene/Si Heterostructures for Self-Powered and Broadband Photodetection

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 812
Author(s):  
Dung-Sheng Tsai ◽  
Ping-Yu Chiang ◽  
Meng-Lin Tsai ◽  
Wei-Chen Tu ◽  
Chi Chen ◽  
...  
Keyword(s):  
Near Infrared ◽  
Bilayer Graphene ◽  
Light Illumination ◽  
Large Area ◽  
Zero Bias ◽  
Graphene Layers ◽  
Si Substrates ◽  
High Uniformity ◽  
Self Powered ◽  
Ultra Shallow Junctions

This work demonstrates a self-powered and broadband photodetector using a heterojunction formed by camphor-based chemical vaper deposition (CVD) bilayer graphene on p-Si substrates. Here, graphene/p-Si heterostructures and graphene layers serve as ultra-shallow junctions for UV absorption and zero bandgap junction materials (<Si bandgap (1.1 eV)) for long-wave near-infrared (LWNIR) absorption, respectively. According to the Raman spectra and large-area (16 × 16 μm2) Raman mapping, a low-defect, >95% coverage bilayer and high-uniformity graphene were successfully obtained by camphor-based CVD processes. Furthermore, the carrier mobility of the camphor-based CVD bilayer graphene at room temperature is 1.8 × 103 cm2/V·s. Due to the incorporation of camphor-based CVD graphene, the graphene/p-Si Schottky junctions show a good rectification property (rectification ratio of ~110 at ± 2 V) and good performance as a self-powered (under zero bias) photodetector from UV to LWNIR. The photocurrent to dark current ratio (PDCR) value is up to 230 at 0 V under white light illumination, and the detectivity (D*) is 8 × 1012 cmHz1/2/W at 560 nm. Furthermore, the photodetector (PD) response/decay time (i.e., rise/fall time) is ~118/120 μs. These results support the camphor-based CVD bilayer graphene/Si Schottky PDs for use in self-powered and ultra-broadband light detection in the future.

Fabrication of Si1-xGex layer on Si substrate by Screen-Printing

MRS Advances ◽  
2019 ◽  
Vol 4 (13) ◽  
pp. 749-754 ◽  
Author(s):  
Masahiro Nakahara ◽  
Moeko Matsubara ◽  
Shota Suzuki ◽  
Shogo Fukami ◽  
Marwan Dhamrin ◽  
...  
Keyword(s):  
Screen Printing ◽  
Sige Layer ◽  
Phase Region ◽  
Si Substrate ◽  
Large Area ◽  
X Ray ◽  
Si Substrates ◽  
The Impact ◽  
Thick Layers ◽  
Metallization Process

AbstractThe impact of the Al and Ge ratio in the Al-Ge pastes are investigated for fabricating the single crystalline Si1-xGex thick layers on large area Si substrates by screen-printing metallization process. From X-ray reciprocal space maps, Ge fraction in the fabricated Si1-xGex thick layers are found to increase up to 40% with increasing the Ge ratio in the Al-Ge pastes. On the other hand, the interface of the Si and Si1-xGex layers are getting winding with increasing the Ge ratio in the Al-Ge pastes. The Al-Si-Ge phase diagram indicated that uniform SiGe layer can be fabricated by adjusting the Al-Ge ratio in the pastes within the liquid phase region.

Threading Dislocation Densities in GaAs Grown on Reduced Area Si Substrates

1993 ◽  
Vol 308 ◽  
Author(s):  
J. Knall ◽  
L.T. Romano ◽  
D.K. Biegelsen ◽  
R.D. Bringans
Keyword(s):  
Side Wall ◽  
Heat Treatments ◽  
Threading Dislocation ◽  
Large Area ◽  
Plan View ◽  
Si Substrates ◽  
Gaas On Si ◽  
Dislocation Densities ◽  
Side Walls ◽  
Wall Growth

ABSTRACTWe have studied the possibilities of reducing the threading dislocation (TD) density in GaAs on Si using free side wall growth on patterned Si substrates and/or using a soft ZnSe interlayer in combination with post growth annealing procedures. TD densities were accurately determined using large area plan view TEM and were found to be unaffected by proximity to free side walls and by the ZnSe interlayer. Post growth heat treatments led to a factor of ∼2 reduction in TD density and to bunching of dislocations throughout the thickness of the film.

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