scholarly journals High-efficiency black silicon interdigitated back contacted solar cells on p-type and n-type c-Si substrates

2015 ◽  
Vol 23 (11) ◽  
pp. 1448-1457 ◽  
Author(s):  
Pablo Ortega ◽  
Eric Calle ◽  
Guillaume von Gastrow ◽  
Päivikki Repo ◽  
David Carrió ◽  
...  
2016 ◽  
Vol 4 (42) ◽  
pp. 16410-16417 ◽  
Author(s):  
Myoung Hee Yun ◽  
Jae Won Kim ◽  
Song Yi Park ◽  
Dong Suk Kim ◽  
Bright Walker ◽  
...  

The first high-efficiency hybrid solar cell of its type comprising p-type silicon with an organic n-type C60 layer is demonstrated.


2013 ◽  
Vol 23 (1) ◽  
pp. 69-77 ◽  
Author(s):  
Juan M. López-González ◽  
Isidro Martín ◽  
Pablo Ortega ◽  
Albert Orpella ◽  
Ramon Alcubilla

2006 ◽  
Vol 910 ◽  
Author(s):  
Qi Wang ◽  
Matt P. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Yanfa Yan ◽  
...  

AbstractWe have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.


2017 ◽  
Vol 32 (2) ◽  
pp. 025005 ◽  
Author(s):  
Huong Thi Thanh Nguyen ◽  
Nagarajan Balaji ◽  
Cheolmin Park ◽  
Nguyen Minh Triet ◽  
Anh Huy Tuan Le ◽  
...  

1989 ◽  
Vol 66 (2) ◽  
pp. 915-919 ◽  
Author(s):  
Masafumi Yamaguchi ◽  
Chikara Amano ◽  
Yoshio Itoh

2021 ◽  
Vol 233 ◽  
pp. 111409
Author(s):  
Jiahui Xu ◽  
Cheng Chen ◽  
Cui Liu ◽  
Jia Chen ◽  
Zhifeng Liu ◽  
...  

Author(s):  
Quanyuan Shang ◽  
Walter Seaman ◽  
Mike Whitney ◽  
Mark George ◽  
John Madocks ◽  
...  

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