Cycle breaking and longest path in channel routing problem

1989 ◽  
Vol 72 (11) ◽  
pp. 20-28 ◽  
Author(s):  
Takashi Shimamoto ◽  
Akio Sakamoto
Keyword(s):  
Channel Routing ◽  
Routing Problem ◽  
Longest Path

scholarly journals An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

VLSI Design ◽  
1994 ◽  
Vol 1 (3) ◽  
pp. 233-242 ◽  
Author(s):  
Xiaoyu Song
Keyword(s):  
Routing Algorithm ◽  
Difficult Problem ◽  
Layout Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Vlsi Layout ◽  
Channel Density ◽  
Optimum Algorithm ◽  
Important Time ◽  
Optimum Channel

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

scholarly journals On the restrictive channel thickness estimation

2007 ◽  
Vol 20 (3) ◽  
pp. 499-506
Author(s):  
Iskandar Karapetyan
Keyword(s):  
Positive Integer ◽  
Heuristic Algorithms ◽  
Clique Number ◽  
Directed Path ◽  
Channel Routing ◽  
Routing Problem ◽  
Thickness Estimation ◽  
Channel Thickness ◽  
Np Complete ◽  
Routing Method

Channel routing is an important phase of physical design of LSI and VLSI chips. The channel routing method was first proposed by Akihiro Hashimoto and James Stevens [1]. The method was extensively studied by many authors and applied to different technologies. At present there are known many effective heuristic algorithms for channel routing. A. LaPaugh [2] proved that the restrictive routing problem is NP-complete. In this paper we prove that for every positive integer k there is a restrictive channel C for which ?(C)>? (HG)+L(VG)+k, where ? (C) is the thickness of the channel, ?(HG) is clique number of the horizontal constraints graph HG and L(VG) is the length of the longest directed path in the vertical constraints graph VG.

Algorithms for Generating Random Channel Instances for Channel Routing Problem

2010 ◽  
Vol 1 (1) ◽  
pp. 106 ◽  
Author(s):  
Achira Pal ◽  
Tarak N. Mandal ◽  
Rajat K. Pal ◽  
Debojit Kundu ◽  
Alak K. Datta
Keyword(s):  
Channel Routing ◽  
Routing Problem

Generation of random channel specifications for channel routing problem

2008 ◽  
Author(s):  
Achira Pal ◽  
Tarak N. Mandal ◽  
Alak K. Datta ◽  
Debojit Kundu ◽  
Rajat K. Pal
Keyword(s):  
Channel Routing ◽  
Routing Problem

INTEGRATED CIRCUIT CHANNEL ROUTING USING A PARETO-OPTIMAL GENETIC ALGORITHM

2012 ◽  
Vol 21 (05) ◽  
pp. 1250041
Author(s):  
THEODORE W. MANIKAS
Keyword(s):  
Integrated Circuit ◽  
Routing Algorithm ◽  
Signal Propagation ◽  
Pareto Optimal ◽  
Signal Delay ◽  
Integrated Circuit Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Propagation Delays ◽  
Optimal Approach

An important part of the integrated circuit design process is the channel routing stage, which determines how to interconnect components that are arranged in sets of rows. The channel routing problem has been shown to be NP-complete, thus this problem is often solved using genetic algorithms. The traditional objective for most channel routers is to minimize total area required to complete routing. However, another important objective is to minimize signal propagation delays in the circuit. This paper describes the development of a genetic channel routing algorithm that uses a Pareto-optimal approach to accommodate both objectives. When compared to the traditional channel routing approach, the new channel router produced layouts with decreased signal delay, while still minimizing routing area.

scholarly journals Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing

VLSI Design ◽  
1998 ◽  
Vol 7 (1) ◽  
pp. 73-84
Author(s):  
Shashidhar Thakur ◽  
Kai-Yuan Chao ◽  
D. F. Wong
Keyword(s):  
Optimal Algorithm ◽  
Vlsi Circuits ◽  
Vertical Layer ◽  
Channel Routing ◽  
Routing Problem ◽  
Circuit Performance ◽  
Layer Assignment

With the increasing density of VLSI circuits, the interconnection wires are getting packed even closer. This has increased the effect of interaction between these wires on circuit performance and hence, the importance of controlling crosstalk. We consider the gridded channel routing problem where, specifically, the channel has 3 routing layers in the VHV configuration. Given a horizontal track assignment for the nets, we present an optimal algorithm for minimizing the crosstalk between vertical wiring segments in the channel by finding an optimal vertical layer assignment for them. We give an algorithm that minimizes total crosstalk between vertical wires on the same V layer on adjacent columns of the grid in O(ν logν) time using O(ν) memory, where the channel has ν columns. We then extend this algorithm to consider crosstalk between wires in nonadjacent columns and between wires on different layers. Finally, we show how our algorithms can be extended to take crosstalk tolerance specifications for nets into account.

scholarly journals Greedy Segmented Channel Router

VLSI Design ◽  
1996 ◽  
Vol 5 (1) ◽  
pp. 11-21
Author(s):  
Dinesh Bhatia ◽  
V. Shankar
Keyword(s):  
Arbitrary Number ◽  
Efficient Solution ◽  
Channel Routing ◽  
Routing Problem ◽  
Greedy Approach

An efficient solution to the generalized detailed routing problem in segmented channels for row-based FPGAs is presented. A generalized detailed routing allows routing of each connection using an arbitrary number of tracks, i.e., doglegs are allowed. This approach is different from the normally followed method where each connection is routed on a single straight track. We present a router that performs generalized segmented channel routing using a greedy approach to route channels. The router also renders itself to limited tolerance against faults in the routing architecture.

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