scholarly journals Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing

VLSI Design ◽  
1998 ◽  
Vol 7 (1) ◽  
pp. 73-84
Author(s):  
Shashidhar Thakur ◽  
Kai-Yuan Chao ◽  
D. F. Wong
Keyword(s):  
Optimal Algorithm ◽  
Vlsi Circuits ◽  
Vertical Layer ◽  
Channel Routing ◽  
Routing Problem ◽  
Circuit Performance ◽  
Layer Assignment

With the increasing density of VLSI circuits, the interconnection wires are getting packed even closer. This has increased the effect of interaction between these wires on circuit performance and hence, the importance of controlling crosstalk. We consider the gridded channel routing problem where, specifically, the channel has 3 routing layers in the VHV configuration. Given a horizontal track assignment for the nets, we present an optimal algorithm for minimizing the crosstalk between vertical wiring segments in the channel by finding an optimal vertical layer assignment for them. We give an algorithm that minimizes total crosstalk between vertical wires on the same V layer on adjacent columns of the grid in O(ν logν) time using O(ν) memory, where the channel has ν columns. We then extend this algorithm to consider crosstalk between wires in nonadjacent columns and between wires on different layers. Finally, we show how our algorithms can be extended to take crosstalk tolerance specifications for nets into account.

scholarly journals An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

VLSI Design ◽  
1994 ◽  
Vol 1 (3) ◽  
pp. 233-242 ◽  
Author(s):  
Xiaoyu Song
Keyword(s):  
Routing Algorithm ◽  
Difficult Problem ◽  
Layout Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Vlsi Layout ◽  
Channel Density ◽  
Optimum Algorithm ◽  
Important Time ◽  
Optimum Channel

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

scholarly journals On the restrictive channel thickness estimation

2007 ◽  
Vol 20 (3) ◽  
pp. 499-506
Author(s):  
Iskandar Karapetyan
Keyword(s):  
Positive Integer ◽  
Heuristic Algorithms ◽  
Clique Number ◽  
Directed Path ◽  
Channel Routing ◽  
Routing Problem ◽  
Thickness Estimation ◽  
Channel Thickness ◽  
Np Complete ◽  
Routing Method

Channel routing is an important phase of physical design of LSI and VLSI chips. The channel routing method was first proposed by Akihiro Hashimoto and James Stevens [1]. The method was extensively studied by many authors and applied to different technologies. At present there are known many effective heuristic algorithms for channel routing. A. LaPaugh [2] proved that the restrictive routing problem is NP-complete. In this paper we prove that for every positive integer k there is a restrictive channel C for which ?(C)>? (HG)+L(VG)+k, where ? (C) is the thickness of the channel, ?(HG) is clique number of the horizontal constraints graph HG and L(VG) is the length of the longest directed path in the vertical constraints graph VG.

Algorithms for Generating Random Channel Instances for Channel Routing Problem

2010 ◽  
Vol 1 (1) ◽  
pp. 106 ◽  
Author(s):  
Achira Pal ◽  
Tarak N. Mandal ◽  
Rajat K. Pal ◽  
Debojit Kundu ◽  
Alak K. Datta
Keyword(s):  
Channel Routing ◽  
Routing Problem

Generation of random channel specifications for channel routing problem

2008 ◽  
Author(s):  
Achira Pal ◽  
Tarak N. Mandal ◽  
Alak K. Datta ◽  
Debojit Kundu ◽  
Rajat K. Pal
Keyword(s):  
Channel Routing ◽  
Routing Problem

scholarly journals The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms

VLSI Design ◽  
2002 ◽  
Vol 14 (2) ◽  
pp. 123-141 ◽  
Author(s):  
Albert Y. Zomaya ◽  
Roger Karpin ◽  
Stephan Olariu
Keyword(s):  
Genetic Algorithms ◽  
Computer Aided Design ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Heuristic Algorithms ◽  
Classical Problem ◽  
Vlsi Circuits ◽  
Single Chip ◽  
Routing Problem ◽  
Single Row

With the advent of VLSI technology, circuits with more than one million transistors have been integrated onto a single chip. As the complexity of ICs grows, the time and money spent on designing the circuits become more important. A large, often dominant, part of the cost and time required to design an IC is consumed in the routing operation. The routing of carriers, such as in IC chips and printed circuit boards, is a classical problem in Computer Aided Design. With the complexity inherent in VLSI circuits, high performance routers are necessary. In this paper, a crucial step in the channel routing technique, the single row routing (SRR) problem, is considered. First, we discuss the relevance of SRR in the context of the general routing problem. Secondly, we show that heuristic algorithms are far from solving the general problem. Next, we introduce evolutionary computation, and, in particular, genetic algorithms (GAs) as a justifiable method in solving the SRR problem. Finally, an efficient O (nk) complexity technique based on GAs heuristic is obtained to solve the general SRR problem containing n nodes. Experimental results show that the algorithm is faster and can often generate better results than many of the leading heuristics proposed in the literature.

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