A comprehensive comparative study of the performance of carbon‐ and copper‐based interconnects in ultra‐large‐scale integrated circuits

2021 ◽  
Author(s):  
Majid Sanaeepur ◽  
Ali Mahmoudi
Keyword(s):  
Integrated Circuits ◽  
Comparative Study ◽  
Large Scale

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

Electron microscopy study of reactively sputter-deposited Ti/N films on silicon

1992 ◽  
Vol 50 (2) ◽  
pp. 1362-1363
Author(s):  
V. C. Kannan ◽  
A. K. Singh ◽  
R. B. Irwin ◽  
S. Chittipeddi ◽  
F. D. Nkansah ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Hexagonal Phase ◽  
Microscopy Study ◽  
Electron Microscopy Study ◽  
Process Conditions ◽  
Tin Films ◽  
Wide Range ◽  
Fcc Phase ◽  
Circuits Vlsi

Titanium nitride (TiN) films have historically been used as diffusion barrier between silicon and aluminum, as an adhesion layer for tungsten deposition and as an interconnect material etc. Recently, the role of TiN films as contact barriers in very large scale silicon integrated circuits (VLSI) has been extensively studied. TiN films have resistivities on the order of 20μ Ω-cm which is much lower than that of titanium (nearly 66μ Ω-cm). Deposited TiN films show resistivities which vary from 20 to 100μ Ω-cm depending upon the type of deposition and process conditions. TiNx is known to have a NaCl type crystal structure for a wide range of compositions. Change in color from metallic luster to gold reflects the stabilization of the TiNx (FCC) phase over the close packed Ti(N) hexagonal phase. It was found that TiN (1:1) ideal composition with the FCC (NaCl-type) structure gives the best electrical property.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy

2004 ◽  
Author(s):  
H.W. Ho ◽  
J.C.H. Phang ◽  
A. Altes ◽  
L.J. Balk
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Large Scale

Abstract In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

Consequences of the COVID‐19 pandemic on the postpartum course: Lessons learnt from a large‐scale comparative study in a teaching hospital

2021 ◽  
Vol 153 (2) ◽  
pp. 315-321
Author(s):  
Nir Kugelman ◽  
Mirit Toledano‐Hacohen ◽  
Debjyoti Karmakar ◽  
Yakir Segev ◽  
Eiman Shalabna ◽  
...  
Keyword(s):  
Comparative Study ◽  
Teaching Hospital ◽  
Large Scale ◽  
Lessons Learnt

Hydrogen Etching Effects During Plasma Doping Processes and Impact on Shallow Junction Formation

1995 ◽  
Vol 396 ◽  
Author(s):  
Shu Qin ◽  
James D. Bernstein ◽  
Chung Chan
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Impurity Profile ◽  
Device Structure ◽  
Hydrogen Etching ◽  
Shallow Junction ◽  
Dopant Profile ◽  
Plasma Doping ◽  
Junction Formation ◽  
Hydrogen Radicals

AbstractHydrogen etching effects in plasma ion implantation (PII) doping processes alter device structure and implant dopant profile and reduce the retained implant dose. This has particular relevance to the shallow junction devices of ultra large scale integrated circuits (ULSI). Hydrogen etching of semiconductor materials including Si, poly-Si, SiO2, Al, and photoresist films have been investigated. The effects of varying different PII process parameters are presented. The experimental data show that the spontaneous etching by hydrogen radicals enhanced by ion bombardment is responsible for the etching phenomena. A computer simulation is used to predict the as-implanted impurity profile and the retained implant dose for a shallow junction doping when the etching effect is considered.

Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing

MRS Bulletin ◽  
1993 ◽  
Vol 18 (6) ◽  
pp. 46-51 ◽  
Author(s):  
S.P. Murarka ◽  
J. Steigerwald ◽  
R.J. Gutmann
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Access Time ◽  
Gigascale Integration ◽  
Interlayer Dielectric ◽  
Application Specific Integrated Circuits ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Application Specific

Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.

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