A comparative study of low-noise logic cells for mixed mode integrated circuits

2002 ◽  
Author(s):  
E. Albuquerque ◽  
M. Silva
Keyword(s):  
Integrated Circuits ◽  
Comparative Study ◽  
Mixed Mode ◽  
Low Noise ◽  
Logic Cells

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

scholarly journals Optimization of spaceflight millimeter-wave impedance matching networks using laser trimming

2021 ◽  
pp. 1-7
Author(s):  
K. Parow-Souchon ◽  
D. Cuadrado-Calle ◽  
S. Rea ◽  
M. Henry ◽  
M. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Millimeter Wave ◽  
Impedance Matching ◽  
Wave Impedance ◽  
Low Noise ◽  
Device Performance ◽  
Interface Circuits ◽  
Interface Circuit ◽  
Noise Amplifier

Abstract Realizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

Single-Crystalline and Bamboo Al Lines Fabricated by Graphoepitaxy: Microstructure and 1/f Noise Measurements

1996 ◽  
Vol 428 ◽  
Author(s):  
Marc J.C. Van Den Homberg ◽  
A. H. Verbruggen ◽  
P. F. A. Alkemade ◽  
S. Radelaar
Keyword(s):  
Integrated Circuits ◽  
Grain Boundaries ◽  
Low Noise ◽  
Dc Magnetron Sputtering ◽  
Rapid Thermal Anneal ◽  
Single Crystalline ◽  
Noise Measurements ◽  
Scaling Down ◽  
Sputter Deposited

AbstractThe continuing scaling-down of integrated circuits leads to increased metallization reliability problems, especially electromigration. We used 1/f noise measurements to study the relation between electromigration and microstructure. These measurements are very sensitive to the microstructural attributes, such as grain boundaries and dislocations. Al lines were grown by graphoepitaxy: First, a pure Al film was grown by dc magnetron sputtering on a groove pattern etched into a SiO2 substrate. The growth was then followed by an in situ rapid thermal anneal that resulted in a complete filling of the grooves with Al. These Al lines were carefully characterized with SEM and Backscatter Kikuchi Diffraction. Depending on the presence of a temperature gradient during the anneal, the lines were either nearly single-crystalline or bamboo with one grain per ∼ 3 μm. The resistivity was ∼ 2.8 μΩcm, only slightly higher than for bulk Al. We measured the 1/f noise with the two-channel ac technique at RT. We found in both bamboo as well as the single-crystalline lines a very low noise intensity; a factor two lower than in conventionally sputter deposited and annealed Al lines. No clear difference between the noise spectra of the bamboo and the single-crystalline lines was observed. We concluded that grain boundaries are not the only contributor to 1/f noise; other types of defects must play a role as well.

A Comparative Study for the Backside Illumination (BSI) Technology Using Bonding Wafer Cleaning Process for Advanced CMOS Image Sensor

2012 ◽  
Vol 195 ◽  
pp. 75-78
Author(s):  
Chung Kyung Jung ◽  
Sung Wook Joo ◽  
Seoung Hun Jeong ◽  
Sang Wook Ryu ◽  
Han Choon Lee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Comparative Study ◽  
Quantum Efficiency ◽  
Wafer Bonding ◽  
Image Sensor ◽  
Silicon On Insulator ◽  
Cleaning Process ◽  
Electrochemical Systems ◽  
Wafer Cleaning ◽  
Direct Wafer Bonding

Over the last decades, the concept of backside illumination (BSI) sensors has become one of the leading solutions to optical challenges such as improved quantum efficiency (QE), and cross-talk, respectively [1-. Direct wafer bonding is a method for fabricating advanced substrates for micro-electrochemical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer.

Ultra-low Residue Flux Applications in RF Front-End Packages

2020 ◽  
Vol 2020 (1) ◽  
pp. 000125-000130
Author(s):  
Leo Hu ◽  
Sze Pei Lim
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Reflow Process ◽  
Reliability Study ◽  
Rf Switches ◽  
Front End ◽  
Rf Front End ◽  
Package Reliability

Abstract With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

Passive Components for RF-ICs

2012 ◽  
pp. 189-214
Author(s):  
Gianluca Cornetta ◽  
David J. Santos ◽  
José Manuel Vázquez
Keyword(s):  
Integrated Circuits ◽  
Quality Factor ◽  
Silicon Substrate ◽  
Supply Voltage ◽  
Magnetic Behavior ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Fully Integrated ◽  
Core Elements ◽  
Low Supply Voltage

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.

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