2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.
Latest Publications

TOTAL DOCUMENTS

115

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Published By IEEE

1424400066

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 0.8V, 88dB Dual-Channel Audio ΔΣ DAC with Headphone Driver

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705308 ◽

2006 ◽

Cited By ~ 1

Author(s):

Q. Meng ◽

K. Lee ◽

T. Sugimoto ◽

K. Hamashita ◽

K. Takasuka ◽

...

Keyword(s):

Dual Channel

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Through Silicon Via and 3-D Wafer/Chip Stacking Technology

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705326 ◽

2006 ◽

Cited By ~ 49

Author(s):

K. Takahashi ◽

M. Sekiguchi

Keyword(s):

Through Silicon Via

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A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705288 ◽

2006 ◽

Cited By ~ 12

Author(s):

Y. Morita ◽

H. Fujiwara ◽

H. Noguchi ◽

K. Kawakami ◽

J. Miyakoshi ◽

...

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The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705384 ◽

2006 ◽

Cited By ~ 6

Author(s):

H. Noda ◽

T. Tanizaki ◽

T. Gyohten ◽

K. Dosaka ◽

M. Nakajima ◽

...

Keyword(s):

Robust Design ◽

Design Methodology ◽

Massively Parallel ◽

Parallel Processor ◽

The Matrix ◽

Massively Parallel Processor

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Multi-Band (1-6GHz), Sampled, Sliding-IF Receiver with Discrete-Time Filtering in 90nm Digital CMOS Process

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705394 ◽

2006 ◽

Cited By ~ 10

Author(s):

H. Lakdawala ◽

J. Zhan ◽

A. Ravi ◽

S. Anderson ◽

B. Carlton ◽

...

Keyword(s):

Discrete Time ◽

Cmos Process ◽

Digital Cmos ◽

Multi Band

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A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705290 ◽

2006 ◽

Cited By ~ 26

Author(s):

S. Ohbayashi ◽

M. Yabuuchi ◽

K. Nii ◽

Y. Tsukamoto ◽

S. Imaoka ◽

...

Keyword(s):

Design For Manufacturing ◽

Sram Design

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A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decisions

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705374 ◽

2006 ◽

Cited By ~ 4

Author(s):

K.-L. Wong ◽

A. Rylyakov ◽

C.-K. Yang

Keyword(s):

Sampling Receiver

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A High Dynamic Range CMOS Image Sensor with In-Pixel Floating-Node Analog Memory for Pixel Level Integration Time Control

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705294 ◽

2006 ◽

Cited By ~ 7

Author(s):

S.-W. Han ◽

S.-J. Kim ◽

J.-H. Choi ◽

C.-K. Kim ◽

E. Yoon

Keyword(s):

Dynamic Range ◽

High Dynamic Range ◽

Cmos Image Sensor ◽

Image Sensor ◽

Integration Time ◽

Time Control ◽

Analog Memory ◽

High Dynamic

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An Integrated 1.8V to 3.3V Regulated Voltage Doubler Using Active Diodes and Dual-Loop Voltage Follower for Switch-Capacitive Load

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705324 ◽

2006 ◽

Cited By ~ 5

Author(s):

Y.-H. Lam ◽

W.-H. Ki ◽

C.-Y. Tsui

Keyword(s):

Capacitive Load ◽

Voltage Follower ◽

Voltage Doubler

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A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. ◽

10.1109/vlsic.2006.1705396 ◽

2006 ◽

Author(s):

P.-I. Mak ◽

S.-P. U ◽

R. Martins

Keyword(s):

Analog Baseband

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 0.8V, 88dB Dual-Channel Audio ΔΣ DAC with Headphone Driver

Through Silicon Via and 3-D Wafer/Chip Stacking Technology

A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Multi-Band (1-6GHz), Sampled, Sliding-IF Receiver with Discrete-Time Filtering in 90nm Digital CMOS Process

A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decisions

A High Dynamic Range CMOS Image Sensor with In-Pixel Floating-Node Analog Memory for Pixel Level Integration Time Control

An Integrated 1.8V to 3.3V Regulated Voltage Doubler Using Active Diodes and Dual-Loop Voltage Follower for Switch-Capacitive Load

A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.
Latest Publications