2017 IEEE International Conference on IC Design and Technology (ICICDT)
Latest Publications

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9781509045020

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Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993509 ◽

2017 ◽

Cited By ~ 1

Author(s):

Louise De Conti ◽

Thomas Bedecarrats ◽

Maud Vinet ◽

Sorin Cristoloveanu ◽

Philippe Galy

Keyword(s):

Esd Protection ◽

Thin Silicon ◽

Soi Cmos

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FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993499 ◽

2017 ◽

Cited By ~ 1

Author(s):

W. Schwarzenbach ◽

M. Sellier ◽

B.-Y. Nguyen ◽

C. Girard ◽

C. Maleville

Keyword(s):

Cmos Technology

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Innovative and 3D stacking Micro Electro Mechanical Systems (I-MEMS) for power saving

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993518 ◽

2017 ◽

Cited By ~ 1

Author(s):

Kiyoshi Mori ◽

Giang Dao ◽

Ziep Tran ◽

Michael Ramon ◽

Jason Woo ◽

...

Keyword(s):

Mechanical Systems ◽

Power Saving ◽

Micro Electro Mechanical Systems ◽

3D Stacking

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Low power Adiabatic Logic based on 2PC2AL

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993517 ◽

2017 ◽

Cited By ~ 1

Author(s):

Mei Han ◽

Yasuhiro Takahashi ◽

Toshikazu Sekine

Keyword(s):

Low Power ◽

Adiabatic Logic

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SOI CMOS technology for quantum information processing

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993523 ◽

2017 ◽

Author(s):

L. Hutin ◽

B. Bertrand ◽

R. Maurand ◽

M. Urdampilleta ◽

B. Jadot ◽

...

Keyword(s):

Information Processing ◽

Quantum Information ◽

Quantum Information Processing ◽

Cmos Technology ◽

Soi Cmos

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Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993500 ◽

2017 ◽

Author(s):

D.H. Triyoso ◽

G.R. Mulfinger ◽

K. Hempel ◽

H. Tao ◽

F. Koehler ◽

...

Keyword(s):

Atomic Layer ◽

Metal Gate ◽

High K ◽

Low K

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Statistical circuit performance dependency analysis via sparse relevance kernel machine

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993507 ◽

2017 ◽

Cited By ~ 2

Author(s):

Honghuang Lin ◽

Asad M. Khan ◽

Peng Li

Keyword(s):

Dependency Analysis ◽

Circuit Performance ◽

Kernel Machine

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FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993513 ◽

2017 ◽

Cited By ~ 5

Author(s):

O. Weber

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Iot Applications

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III–V-based low power CMOS devices on Si platform

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993497 ◽

2017 ◽

Author(s):

S. Takagi ◽

D. H. Ahn ◽

T. Gotow ◽

M. Noguchi ◽

K. Nishi ◽

...

Keyword(s):

Low Power ◽

Low Power Cmos

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Layout engineering to suppress hysteresis of negative capacitance FinFET

2017 IEEE International Conference on IC Design and Technology (ICICDT) ◽

10.1109/icicdt.2017.7993498 ◽

2017 ◽

Author(s):

Eunah Ko ◽

Jaesung Jo ◽

Changhwan Shin ◽

Bich-Yen Nguyen

Keyword(s):

Negative Capacitance

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2017 IEEE International Conference on IC Design and Technology (ICICDT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies

FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond

Innovative and 3D stacking Micro Electro Mechanical Systems (I-MEMS) for power saving

Low power Adiabatic Logic based on 2PC2AL

SOI CMOS technology for quantum information processing

Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor

Statistical circuit performance dependency analysis via sparse relevance kernel machine

FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications

III–V-based low power CMOS devices on Si platform

Layout engineering to suppress hysteresis of negative capacitance FinFET

2017 IEEE International Conference on IC Design and Technology (ICICDT)
Latest Publications