2015 IEEE 24th North Atlantic Test Workshop
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

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(FIVE YEARS 0)

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9781467374170

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Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.8 ◽

2015 ◽

Cited By ~ 2

Author(s):

Mohamed Hanafy ◽

Hazem Said ◽

Ayman M. Wahba

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Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.16 ◽

2015 ◽

Cited By ~ 2

Author(s):

Amin Vali ◽

Nicola Nicolici

Keyword(s):

Silicon Debug

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Hybrid Hierarchical and Modular Tests for SoC Designs

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.9 ◽

2015 ◽

Cited By ~ 4

Author(s):

Guoliang Li ◽

Jun Qian ◽

Qinfu Yang ◽

Yuan Zuo ◽

Rui Li ◽

...

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At-Speed Path Delay Test

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.13 ◽

2015 ◽

Cited By ~ 1

Author(s):

Swati Chakraborty ◽

D.M.H. Walker

Keyword(s):

Path Delay ◽

Delay Test ◽

Path Delay Test

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An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.19 ◽

2015 ◽

Author(s):

Jennifer Dworak ◽

Ping Gui ◽

Qutaiba Khasawneh

Keyword(s):

Industrial Case Study ◽

Mixed Signal ◽

Concurrent Testing

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Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.14 ◽

2015 ◽

Cited By ~ 4

Author(s):

Rawad Al-Haddad ◽

Rashad S. Oreifej ◽

Ramtin Zand ◽

Abdel Ejnioui ◽

Ronald F. DeMara

Keyword(s):

Reconfigurable Logic ◽

Radiation Induced

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2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.7 ◽

2015 ◽

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Author index

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.11 ◽

2015 ◽

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Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.15 ◽

2015 ◽

Cited By ~ 3

Author(s):

Baohu Li ◽

Vishwani D. Agrawal

Keyword(s):

Multivalued Logic ◽

Soc Testing

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[Copyright notice]

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.3 ◽

2015 ◽

Keyword(s):

Download Full-text

2015 IEEE 24th North Atlantic Test Workshop
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug

Hybrid Hierarchical and Modular Tests for SoC Designs

At-Speed Path Delay Test

An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices

Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics

Table of contents

Author index

Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing

[Copyright notice]

Export Citation Format

2015 IEEE 24th North Atlantic Test WorkshopLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug

Hybrid Hierarchical and Modular Tests for SoC Designs

At-Speed Path Delay Test

An Industrial Case Study: PaRent (Parallel &amp; Concurrent) Testing for Complex Mixed-Signal Devices

Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics

Table of contents

Author index

Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing

[Copyright notice]

2015 IEEE 24th North Atlantic Test Workshop
Latest Publications

An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices