Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
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Published By CRC Press

9781315217819

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Timing-Aware ATPG

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-4 ◽

2017 ◽

pp. 49-69

Author(s):

Kassab Mark ◽

Nadeau-Dostie Benoit ◽

Lin Xijiang

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K Longest Paths

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-3 ◽

2017 ◽

pp. 23-48

Author(s):

M. (Hank) Walker Duncan

Keyword(s):

Longest Paths

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Small-Delay Defect Coverage Metrics

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-13 ◽

2017 ◽

pp. 185-210

Author(s):

Devta-Prasanna Narendra ◽

K. Goel Sandeep

Keyword(s):

Defect Coverage ◽

Coverage Metrics ◽

Small Delay

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Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-10 ◽

2017 ◽

pp. 147-160

Author(s):

K. Goel Sandeep ◽

Devta-Prasanna Narendra

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects

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Faster-than-at-Speed Test for Screening Small-Delay Defects

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-6 ◽

2017 ◽

pp. 73-94

Author(s):

Ahmed Nisar ◽

Tehranipoor Mohammad

Keyword(s):

Speed Test ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects

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Fundamentals of Small-Delay Defect Testing

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-1 ◽

2017 ◽

pp. 1-20

Author(s):

M. Reddy Sudhakar ◽

Maxwell Peter

Keyword(s):

Small Delay

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Circuit Path Grading Considering Layout, Process Variations, and Cross Talk

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-7 ◽

2017 ◽

pp. 95-116

Author(s):

Peng Ke ◽

Yilmaz Mahmut ◽

Tehranipoor Mohammad

Keyword(s):

Cross Talk ◽

Process Variations

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Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-11 ◽

2017 ◽

pp. 161-182

Author(s):

K. Goel Sandeep ◽

Chakrabarty Krish

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Circuit Topology ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects

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Output Deviations-Based SDD Testing

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-9 ◽

2017 ◽

pp. 119-146

Author(s):

Yilmaz Mahmut

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Conclusion

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits ◽

10.1201/b15549-14 ◽

2017 ◽

pp. 211-214

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Testing for Small-Delay Defects in Nanoscale CMOS Integrated CircuitsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By CRC Press

Timing-Aware ATPG

K Longest Paths

Small-Delay Defect Coverage Metrics

Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects

Faster-than-at-Speed Test for Screening Small-Delay Defects

Fundamentals of Small-Delay Defect Testing

Circuit Path Grading Considering Layout, Process Variations, and Cross Talk

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

Output Deviations-Based SDD Testing

Conclusion

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
Latest Publications