2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Latest Publications

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Published By IEEE

9781424464654, 9781424464661

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Effect of Reordering Internal Messages in MPI Broadcast According to the Load Imbalance

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.14 ◽

2008 ◽

Author(s):

Takesi Soga ◽

Takeshi Nanri ◽

Motoyoshi Kurokawa ◽

Kazuaki Murakami

Keyword(s):

Load Imbalance

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Copyright Page

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.3 ◽

2008 ◽

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Unified Programming Environment for Heterogeneous Distributed Parallel Systems

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.16 ◽

2008 ◽

Author(s):

Shoichi Hirasawa ◽

Hiroki Honda

Keyword(s):

Parallel Systems ◽

Programming Environment

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Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.7 ◽

2008 ◽

Author(s):

José L. Ayala ◽

Pablo G. Del Valle ◽

David Atienza

Keyword(s):

Reliability Analysis ◽

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Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.15 ◽

2008 ◽

Cited By ~ 2

Author(s):

Noboru Tanabe ◽

Hironori Nakajo

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Title Page iii

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.2 ◽

2008 ◽

Keyword(s):

Title Page

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Introspection-Based Fault Tolerance for COTS-Based High-Capability Computation in Space

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.11 ◽

2008 ◽

Cited By ~ 1

Author(s):

Mark L. James ◽

Andrew A. Shapiro ◽

Paul L. Springer ◽

Hans P. Zima

Keyword(s):

Fault Tolerance

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Low-Power and High-Performance Communication Mechanism for Dependable Embedded Systems

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.8 ◽

2008 ◽

Cited By ~ 5

Author(s):

Toshihiro Hanawa ◽

Taisuke Boku ◽

Shin'ichi Miura ◽

Takayuki Okamoto ◽

Mitsuhisa Sato ◽

...

Keyword(s):

Embedded Systems ◽

Low Power ◽

High Performance ◽

Communication Mechanism ◽

Dependable Embedded Systems

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A PLD Architecture for High Performance Computing

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.12 ◽

2008 ◽

Cited By ~ 1

Author(s):

Naoki Hirakawa ◽

Masanori Yoshihara ◽

Kazuya Tanigawa ◽

Tetsuo Hironaka ◽

Masayuki Sato

Keyword(s):

High Performance Computing ◽

High Performance ◽

Performance Computing

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The Shape of Things to Come: Future Potential of "Heavy Node" Multi-Core HPC Architectures

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems ◽

10.1109/iwia.2008.13 ◽

2008 ◽

Author(s):

Peter M. Kogge

Keyword(s):

Future Potential ◽

To Come

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2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Effect of Reordering Internal Messages in MPI Broadcast According to the Load Imbalance

Copyright Page

Unified Programming Environment for Heterogeneous Distributed Parallel Systems

Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network

Title Page iii

Introspection-Based Fault Tolerance for COTS-Based High-Capability Computation in Space

Low-Power and High-Performance Communication Mechanism for Dependable Embedded Systems

A PLD Architecture for High Performance Computing

The Shape of Things to Come: Future Potential of "Heavy Node" Multi-Core HPC Architectures

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Latest Publications