Low-Power and High-Performance Communication Mechanism for Dependable Embedded Systems

2008 ◽  
Author(s):  
Toshihiro Hanawa ◽  
Taisuke Boku ◽  
Shin'ichi Miura ◽  
Takayuki Okamoto ◽  
Mitsuhisa Sato ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance ◽  
Communication Mechanism ◽  
Dependable Embedded Systems

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

2016 ◽  
Vol 65 (7) ◽  
pp. 2313-2324 ◽  
Author(s):  
Keni Qiu ◽  
Qingan Li ◽  
Jingtong Hu ◽  
Weigong Zhang ◽  
Chun Jason Xue
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance ◽  
Loop Tiling

SH-X3 xible SuperH multi-core for high-performance and low-power embedded systems

2007 ◽  
Author(s):  
Shinichi Shibahara ◽  
Masashi Takada ◽  
Tatsuya Kamei ◽  
Kiyoshi Hayase ◽  
Yutaka Yoshida ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance

Write Mode Aware Loop Tiling for High-Performance Low-Power Volatile PCM in Embedded Systems

2020 ◽  
pp. 171-198
Author(s):  
Keni Qiu ◽  
Qingan Li ◽  
Jingtong Hu ◽  
Weigong Zhang ◽  
Chun Jason Xue
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
High Performance ◽  
Loop Tiling

High-Performance and Low-Power Full Color Reflective LCD for New Applications

2019 ◽  
pp. 1411
Author(s):  
Hiroyuki Hakoi ◽  
Ming Ni ◽  
Junichi Hashimoto ◽  
Takashi Sato ◽  
Shinji Shimada ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Color ◽  
New Applications
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