A 1.6-GHz delta-sigma modulated fractional-N frequency synthesizer

2005 ◽  
Author(s):  
Ching-Yuan Yang ◽  
Kuei-Zu Jiang ◽  
Jen-Wen Chen
Keyword(s):  
Frequency Synthesizer ◽  
Delta Sigma

A Type-I $\Delta\Sigma$ Fractional-N Frequency Synthesizer Adopting a New Discrete-Time Loop Filter

2013 ◽  
Vol 23 (10) ◽  
pp. 545-547
Author(s):  
Seungjin Kim ◽  
Joo-Myoung Kim ◽  
In-Young Lee ◽  
Sang-Gug Lee
Keyword(s):  
Discrete Time ◽  
Frequency Synthesizer ◽  
Type I ◽  
Loop Filter ◽  
Delta Sigma ◽  
Time Loop

A novel structure of dithered nested digital delta sigma modulator with low-complexity low-spur for fractional frequency synthesizers

2016 ◽  
Vol 35 (1) ◽  
pp. 157-171 ◽  
Author(s):  
Seyed Ali Sadat Noori ◽  
Ebrahim Farshidi ◽  
Sirus Sadoughi
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Synthesizers ◽  
Linear Feedback ◽  
Hardware Complexity ◽  
Order Error ◽  
Content Type ◽  
First Order ◽  
Fractional Frequency ◽  
Delta Sigma Modulator ◽  
Delta Sigma

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

The Delta-Sigma Modulator of Fractional-N Frequency Synthesizer for Wireless Sensors Network Applications

2014 ◽  
Vol 609-610 ◽  
pp. 1014-1019 ◽  
Author(s):  
Zhi Qiang Gao ◽  
Jin Bao Lan ◽  
Xiao Wei Liu ◽  
Liang Yin
Keyword(s):  
Frequency Synthesizer ◽  
Linear Feedback ◽  
Cmos Process ◽  
Noise Shaping ◽  
Network Applications ◽  
Delta Sigma Modulator ◽  
Multi Stage ◽  
Delta Sigma ◽  
Third Stage ◽  
Feedback Shift Register

This paper presents a design of fractional-N frequency synthesizer with low dithering, which is fabricated in a 130nm CMOS process. A 3rd-order delta-sigma modulator is based on digital multi-stage noise shaping (MASH) structure with its second and third stage dithered by 7-bit linear feedback shift register (LFSR) was designed for the frequency synthesizer, and a long word is used for the first modulator in the MASH structure. The simulation result of the whole frequency synthesizer shows that it can output two-way I/Q signal between 2.28GHz and 2.53GHz, and its spurs are lower than-75dBc.

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