2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
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9781479963843

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Memristor content addressable memory

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880476 ◽

2014 ◽

Cited By ~ 3

Author(s):

Wanlong Chen ◽

Xiao Yang ◽

Frank Z. Wang

Keyword(s):

Content Addressable Memory

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Virtual prototyping of R2D NASIC based FPGA

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880509 ◽

2014 ◽

Author(s):

Ciprian Teodorov ◽

Loic Lagadec

Keyword(s):

Virtual Prototyping

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HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880477 ◽

2014 ◽

Cited By ~ 3

Author(s):

Pilin Junsangsri ◽

Fabrizio Lombardi ◽

Jie Han

Keyword(s):

Programmable Metallization Cell ◽

Memory Design

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Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880501 ◽

2014 ◽

Cited By ~ 4

Author(s):

David Roclin ◽

Olivier Bichler ◽

Christian Gamrat ◽

Jacques-Olivier Klein

Keyword(s):

Neural Networks ◽

Spiking Neural Networks

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A memristor-based TCAM (Ternary Content Addressable Memory) cell

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880478 ◽

2014 ◽

Cited By ~ 7

Author(s):

Pilin Junsangsri ◽

Fabrizio Lombardi ◽

Jie Han

Keyword(s):

Memory Cell ◽

Content Addressable Memory ◽

Ternary Content Addressable Memory

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Minimization of a reversible quantum 2n-to-n BCD priority encoder

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880474 ◽

2014 ◽

Author(s):

Nusrat Jahan Lisa ◽

Hafiz Md. Hasan Babu

Keyword(s):

Priority Encoder

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A standard cell approach for MagnetoElastic NML circuits

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880491 ◽

2014 ◽

Cited By ~ 1

Author(s):

D. Giri ◽

M. Vacca ◽

G. Causapruno ◽

Wenjing Rao ◽

M. Graziano ◽

...

Keyword(s):

Standard Cell

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A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880504 ◽

2014 ◽

Cited By ~ 5

Author(s):

Alireza Goudarzi ◽

Matthew R. Lakin ◽

Darko Stefanovic ◽

Christof Teuscher

Keyword(s):

Fault Tolerant ◽

Digital Logic ◽

Self Assembled

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Pipeline design in spintronic circuits

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880496 ◽

2014 ◽

Cited By ~ 2

Author(s):

Nickvash Kani ◽

Azad Naeemi

Keyword(s):

Pipeline Design

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Energy effective 3D stacked hybrid NEMFET-CMOS caches

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2014.6880506 ◽

2014 ◽

Cited By ~ 1

Author(s):

Mihai Lefter ◽

Marius Enachescu ◽

George Razvan Voicu ◽

Sorin Dan Cotofana

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2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Memristor content addressable memory

Virtual prototyping of R2D NASIC based FPGA

HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design

Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks

A memristor-based TCAM (Ternary Content Addressable Memory) cell

Minimization of a reversible quantum 2n-to-n BCD priority encoder

A standard cell approach for MagnetoElastic NML circuits

A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures

Pipeline design in spintronic circuits

Energy effective 3D stacked hybrid NEMFET-CMOS caches

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Latest Publications