2010 VI Southern Programmable Logic Conference (SPL)
Latest Publications

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Published By IEEE

9781424463091, 9781424463107

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

FPGA based floating-point library for CORDIC algorithms

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483002 ◽

2010 ◽

Cited By ~ 14

Author(s):

Daniel M Munoz ◽

Diego F. Sanchez ◽

Carlos H. Llanos ◽

Mauricio Ayala-Rincon

Keyword(s):

Floating Point

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Implementation of Split-Radix Fast Fourier Transform on FPGA

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483018 ◽

2010 ◽

Cited By ~ 1

Author(s):

Cynthia Watanabe ◽

Carlos Silva ◽

Joel Munoz

Keyword(s):

Fourier Transform ◽

Fast Fourier Transform

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Delay modeling for power noise-aware design in Spartan-3A FPGAs

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483026 ◽

2010 ◽

Author(s):

Judit F. Freijedo ◽

Maria D. Valdes ◽

Maria J. Moure ◽

Lucia Costas ◽

Juan J. Rodriguez-Andina ◽

...

Keyword(s):

Power Noise

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FPGA-based real time processing of the plenoptic wavefront sensor for the european solar telescope (EST)

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483032 ◽

2010 ◽

Cited By ~ 1

Author(s):

Y. Martin ◽

L.F. Rodriguez-Ramos ◽

J. Garcia ◽

J.J. Diaz Garcia ◽

J.M. Rodriguez-Ramos

Keyword(s):

Real Time ◽

Wavefront Sensor ◽

Solar Telescope ◽

Real Time Processing ◽

Time Processing

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An optimized label-broadcast parallel algorithm for connected components labeling

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483030 ◽

2010 ◽

Author(s):

Joao Marcelo Xavier Natario Teixeira ◽

Bernardo Reis ◽

Veronica Teichrieb ◽

Judith Kelner

Keyword(s):

Parallel Algorithm ◽

Connected Components

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Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483003 ◽

2010 ◽

Cited By ~ 7

Author(s):

Guilherme Perin ◽

Daniel G. Mesquita ◽

Fernando L. Herrmann ◽

Joao Baptista Martins

Keyword(s):

Systolic Array ◽

Parallel Implementation ◽

Reconfigurable Hardware ◽

Modular Multiplication ◽

Montgomery Modular Multiplication

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Design and implementation of packet switching capabilities on 10GbE MAC core

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483024 ◽

2010 ◽

Author(s):

Roman A. Arenas ◽

Jorge M. Finochietto ◽

Leonardo M. Rocha

Keyword(s):

Packet Switching ◽

Design And Implementation

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A high performance hardware architecture for the H.264/AVC half-pixel interpolation unit

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5482998 ◽

2010 ◽

Cited By ~ 4

Author(s):

Marcel M. Correa ◽

Mateus T. Schoenknecht ◽

Robson S. Dornelles ◽

Luciano V. Agostini

Keyword(s):

High Performance ◽

Hardware Architecture ◽

Pixel Interpolation

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Protection of microprocessor-based cores for FPL devices

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483008 ◽

2010 ◽

Cited By ~ 1

Author(s):

Luis Parrilla ◽

Encarnacion Castillo ◽

Antonio Garcia ◽

Daniel Gonzalez ◽

Antonio Lloris ◽

...

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Multiprotocol transceiving, Formatting and Temperature monitoring FPGA based unit

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483025 ◽

2010 ◽

Author(s):

Ricardo de Porras Bernacer

Keyword(s):

Temperature Monitoring

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2010 VI Southern Programmable Logic Conference (SPL)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

FPGA based floating-point library for CORDIC algorithms

Implementation of Split-Radix Fast Fourier Transform on FPGA

Delay modeling for power noise-aware design in Spartan-3A FPGAs

FPGA-based real time processing of the plenoptic wavefront sensor for the european solar telescope (EST)

An optimized label-broadcast parallel algorithm for connected components labeling

Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation

Design and implementation of packet switching capabilities on 10GbE MAC core

A high performance hardware architecture for the H.264/AVC half-pixel interpolation unit

Protection of microprocessor-based cores for FPL devices

Multiprotocol transceiving, Formatting and Temperature monitoring FPGA based unit

2010 VI Southern Programmable Logic Conference (SPL)
Latest Publications