A high performance hardware architecture for the H.264/AVC half-pixel interpolation unit

2010 ◽  
Author(s):  
Marcel M. Correa ◽  
Mateus T. Schoenknecht ◽  
Robson S. Dornelles ◽  
Luciano V. Agostini
Keyword(s):  
High Performance ◽  
Hardware Architecture ◽  
Pixel Interpolation

A high performance hardware architecture for multi-frame hierarchical motion estimation

2011 ◽  
Vol 57 (2) ◽  
pp. 794-801 ◽  
Author(s):  
Huong Ho ◽  
Robert Klepko ◽  
Nam Ninh ◽  
Demin Wang
Keyword(s):  
Motion Estimation ◽  
High Performance ◽  
Hardware Architecture

scholarly journals An Efficient MAC Architecture using Multiplier for DSP and DIP Operations

2018 ◽  
Vol 7 (2.16) ◽  
pp. 110
Author(s):  
P Rahul Reddy ◽  
Pandya Vyomal N ◽  
Abhishek Choubey
Keyword(s):  
Signal Processing ◽  
Hearing Aids ◽  
High Performance ◽  
Digital Signal ◽  
Building Blocks ◽  
Hardware Architecture ◽  
Verilog Hdl ◽  
Medical Discipline ◽  
Critical Components ◽  
Wallace Tree Multiplier

DSP operations are very important part of engineering as well as medical discipline. For the designing of DSP operations Multiplication is play important role to perform signal processing operations. Multiplier is one of the critical components in the area of digital signal processing and hearing aids. So the objective is to design an efficient MAC hardware architecture using multiplier with assistance of compressors by conserving less area, power and delay. In this paper, efficient hardware architecture of MAC using a modified Wallace tree multiplier is proposed. The proposed MAC uses multiplier with novel compressor designs and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of 8 bit MAC architecture and their FPGA implementation by Xilinx ISE 14.4 Synthesis Tool on Virtex7 kit have been done. The proposed compressor and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce in terms of area, delay and power. The high performance is obtained by using a new hierarchical structure, these adders are called compressors.  These compressors make the multipliers faster as compared to the conventional design used in Engineering, Science & Technology as well as medical discipline.

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