High Precision Timing with Parabolic Equation Fitting in Narrowband Systems

Timing forms the basis of wireless communication systems. Orthogonal frequency division multiplexing (OFDM) technology has strict requirements for synchronization performance, and timing errors lead to interference between subcarriers and symbols. Although cyclic prefix (CP) can relax the timing requirement, high precision timing is still necessary and can release the pressure on CP. Due to the uncertainty of signal arrival, there is a sampling offset between the sampling sample’s timing and the real timing, which can be large in the narrowband system with a low sampling rate. In this paper, we propose a parabolic equation fitting method to improve the timing precision in narrowband systems that have two times the rate of the Nyquist sampling rate. The proposed timing method is easy to implement, with low additional complexity compared to traditional timing detection and is based on traditional direct correlator output.

Scheduling approach for on-site jobs of service providers

Nowadays the successful operation of a company is unimaginable without fast and reliable communication. As a result, so-called Communication Service Providers play an important role in today’s business life. Their orders have to be carried out promptly and dependably, let them be requests for new installations, modifications, or maintenance tasks. These orders have to be performed at different locations and they often have deadlines or strict starting times. Violating such a timing requirement usually implies penalties. In this paper, scheduling problems arising at a Hungarian service provider are examined. At this company, orders are decomposed into smaller tasks, which can be performed by specially trained personnel. Transportation of these specialists contributes a lot to the costs and to the complexity of their scheduling, as well. The goal is to minimize the overall cost of satisfying all orders within the given time horizon with the available assets of the company. The proposed approach relies on the S-graph framework, which has been applied to various production scheduling problems in the literature. In addition to an unambiguous and sound S-graph model of the examined problem, slight modifications of the scheduling algorithms for cost minimization, and new bounding methods have been developed. Several of such bounds have been provided and tested for performance and scalability over a large number of generated examples. The sensitivity of the approach for certain problem features has also been examined.

Design and Implementation of IEEE 1588 High Precision Clock Synchronization Based on GPS Time Service

In view of PTP high precise timing requirement for many application fields, GPS time service is provided with the advantages of high precision and high stabilization. The principle and timescale of PTP based on GPS are analyzed and discussed. And then a PTP time synchronization platform with GPS-based UTC time is designed and implemented, the correlative key design flowchart is described as well. Finally, the paper gives the experiment results, which show the time synchronization accuracies can reach nanosecond range.

The Design of a 5 GHz Programmable Frequency Divider for Fractional-N Frequency Synthesizer

The design of a high speed programmable frequency divider for fractional-N frequency synthesizer is presented. The programmable divider consists of a divide-by-4/5 dual-modulus prescaler, a 5-bit programmable counter, and a 2-bit swallow counter. A new scheme of reload operation is adopted to reduce the propagation delay of the critical path. The triggering signal for the two counters is selected carefully to mitigate the timing requirement of the mode control signal. The divider is designed in 0.18 um CMOS process. Its division ratio (DR) covers the range from 12 to 127. Post-layout simulations show it can work up to 5 GHz under 1.8 V power supply, while consuming only 9 mW and occupying an area of about 0.06 mm2.

Buffer Planning for IP Placement Using Sliced-LFF

IP cores are widely used in modern SOC designs. Hierarchical design has been employed for the growing design complexity, which stimulates the need for fixed-outline floorplanning. Meanwhile, buffer insertion is usually adopted to meet the timing requirement. In this paper, buffer insertion is considered with a fixed-outline constraint using Less Flexibility First (LFF) algorithm. Compared with Simulated Annealing (SA), our work is able to distinguish geometric differences between two floorplan candidates, even if they have the same topological structure. This is helpful to get a better result for buffer planning since buffer insertion is quite sensitive to a geometric change. We also extend the previous LFF to a more robust version called Sliced-LFF to improve buffer planning. Moreover, a 2-staged LFF framework and a post-greedy procedure are introduced based on our net-classing strategy and finally achieve a significant improvement on the success rate of buffer insertion (40.7% and 37.1% in different feature sizes). Moreover, our work is much faster than SA, since it is deterministic without iterations.