Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology

Different Half-Bridge (HB) converter topologies for an Integrated Voltage Regulator (IVR), which serves as a microprocessor application, were evaluated. The HB circuits were implemented with Stacked Transistors (HBSTs) in a cutting-edge 14 nm CMOS technology node in order to enable the integration on the microprocessor die. Compared to a conventional realization of the HBST, it was found that the Active Neutral-Point Clamped (ANPC) HBST topology with Independent Clamp Switches (ICSs) not only ensured balanced blocking voltages across the series-connected transistors, but also featured a more robust operation and achieved higher efficiencies at high output currents. The IVR achieved a maximum efficiency of 85.3% at an output current of 300 mA and a switching frequency of 50 MHz. At the maximum measured output current of 780 mA, the efficiency was 83.1%. The active part of the IVR (power switches, gate-drivers, and level shifters) realized a high maximum current density of 24.7 A/mm2.

Recent Progress in Rapid-Single-Flux-Quantum Circuits

We describe recent topics of rapid-single-flux-quantum (RSFQ) circuits. Much higher integration and higher-speed operation are required for commercializing the RSFQ circuits in any application. To satisfy this requirement, we measure several kinds of time fluctuations that possibly limit the integration level and operating speed, and introduce the flexible passive transmission line technology including a multicasting transmitter. In addition, we describe our ongoing applications. A multiple-detectors-system is expected to open a new application field of an RSFQ-based analog-to-digital converter and a digital signal processor. As for a microprocessor application, increased number of arithmetic logic units may be effective for enhancing the computing performances.