Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.

Simulation of Stacked Quantum Dot Channels SWS-FET Using Multi-FET ABM Modeling

This paper presents simulation of spatial wavefunction switched (SWS) field-effect transistors (FETs) comprising of two vertically stacked quantum dot channels. An analog behavior model (ABM) was used to compare the experimental I-V characteristics of a fabricated QD-SWS-FET. Each channel consists of two quantum dot layers and are connected to the dedicated drains D2 and D1, respectively. The fabricated SWS-FET has one source and one gate. The ABM simulation models SWS-FET comprising of two independent conventional BSIM FETs with their (W/L) ratios, capacitances and other device parameters. The agreement in simulation and experimental data will advance modeling of SWS based adders, logic gates and SRAMs.

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.

Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs

This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The influence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measurements. The transconductance, output conductance, Early voltage and intrinsic voltage gain have been used as figure of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been obtained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.