Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15nm gate Length

In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (ION), off-current (IOFF), subthreshold swing (SS), drain induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (Vea) and intrinsic gain (Av). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device.

Performance Analysis of TFET and VDSTFET for Low Power Application using the Work Function Engineering

We report a design of TFET which is quite different from conventional TFET. The structure of VTFET is similar to MOSFET but the conducting mechanism is completely different. Vertical TFET is designed perpendicular to the horizontal plane. The switching and carrier transportation mechanism of VTFET is based on the mechanism of the band to band tunneling through a potential barrier and vertical TFET is based on tunneling perpendicular to the device rather than a mechanism like thermionic emission unlike in MOSFET. We have designed a model for the two-dimension structure of V-TFET which consists of the dual-source and single drain. The channel among the drain and gate region is extraordinarily thin. We have plotted the transfer characteristics of V-TFET according to device parameters using TCAD. The comparison of VTFET with DSVTFET is done by using Silvaco TCAD and the effect of source doping, and work function on transfer characteristics of the device is examined by using silvaco TCAD simulations. The proposed device produces a low-off current.

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (VGS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative VGS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (VTH) shift, on-state resistance (RDS-ON) increase, transconductance max (Gm, max) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative VGS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the VTH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.

Effects of Recess Depth Under the Gate Area on the Vth-Shift for Fabricating Normally-Off Field Effect Transistors on AlGaN/GaN Heterostructures

Fabrication of normally-off field effect transistors (FETs) possessed uniform turn-on threshold voltage (Vth) is of special interests. In this work, they were fabricated using dry etching recess techniques under the gate region, with dry etching conditions of extremely low rate. We report how the recess depth under the gate area induced the Vth shift of normally-off FETs on AlGaN/GaN heterostructure, which were fabricated with a 1.5 nm/min etching rate. Chlorine-based inductively coupled plasma (ICP) was applied to perform the etching process for the AlGaN/GaN heterostructure. Devices were fabricated with different recess depths under the gate area, and examined to determine their performances, particularly the dependence of recess time and recess depth on Vth shift. The applied dry etching conditions resulted in a low-damaged and not-rough morphology on the etched surfaces of AlGaN/GaN. Fine controlled and well defined recess depth of the AlGaN/GaN heterostructure under the gate region was achieved with no etch-stop layers. Conventional fabrication processes were applied with the dry etching conditions of extremely low rate to fabricate normally-off MOSFETs of Al2O3/AlGaN/GaN. The achieved Vth of +5.64 V was high positive and the leakage current of off-state was measured as ~10−6 A/mm.

Investigation of Recessed Gate AlGaN/GaN MIS-HEMTs with Double AlGaN Barrier Designs toward an Enhancement-Mode Characteristic

In this work, recessed gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with double AlGaN barrier designs are fabricated and investigated. Two different recessed depths are designed, leading to a 5 nm and a 3 nm remaining bottom AlGaN barrier under the gate region, and two different Al% (15% and 20%) in the bottom AlGaN barriers are designed. First of all, a double hump trans-conductance (gm)–gate voltage (VG) characteristic is observed in a recessed gate AlGaN/GaN MIS-HEMT with a 5 nm remaining bottom Al0.2Ga0.8N barrier under the gate region. Secondly, a physical model is proposed to explain this double channel characteristic by means of a formation of a top channel below the gate dielectric under a positive VG. Finally, the impacts of Al% content (15% and 20%) in the bottom AlGaN barrier and 5 nm/3 nm remaining bottom AlGaN barriers under the gate region are studied in detail, indicating that lowering Al% content in the bottom can increase the threshold voltage (VTH) toward an enhancement-mode characteristic.

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.

Does human P-glycoprotein efflux involve transmembrane alpha helix breakage?

The occluded conformation suggested in a recent article that revealed a new inward-facing conformation for the human P-glycoprotein may not represent the closing of a gate region but instead an artifact derived from lateral compression in a too small sized nanodisc, used to stabilize the transmembrane domains of the transporter.