Early postexercise muscle glycogen recovery is enhanced with a carbohydrate-protein supplement

In the present study, we tested the hypothesis that a carbohydrate-protein (CHO-Pro) supplement would be more effective in the replenishment of muscle glycogen after exercise compared with a carbohydrate supplement of equal carbohydrate content (LCHO) or caloric equivalency (HCHO). After 2.5 ± 0.1 h of intense cycling to deplete the muscle glycogen stores, subjects ( n = 7) received, using a rank-ordered design, a CHO-Pro (80 g CHO, 28 g Pro, 6 g fat), LCHO (80 g CHO, 6 g fat), or HCHO (108 g CHO, 6 g fat) supplement immediately after exercise (10 min) and 2 h postexercise. Before exercise and during 4 h of recovery, muscle glycogen of the vastus lateralis was determined periodically by nuclear magnetic resonance spectroscopy. Exercise significantly reduced the muscle glycogen stores (final concentrations: 40.9 ± 5.9 mmol/l CHO-Pro, 41.9 ± 5.7 mmol/l HCHO, 40.7 ± 5.0 mmol/l LCHO). After 240 min of recovery, muscle glycogen was significantly greater for the CHO-Pro treatment (88.8 ± 4.4 mmol/l) when compared with the LCHO (70.0 ± 4.0 mmol/l; P = 0.004) and HCHO (75.5 ± 2.8 mmol/l; P = 0.013) treatments. Glycogen storage did not differ significantly between the LCHO and HCHO treatments. There were no significant differences in the plasma insulin responses among treatments, although plasma glucose was significantly lower during the CHO-Pro treatment. These results suggest that a CHO-Pro supplement is more effective for the rapid replenishment of muscle glycogen after exercise than a CHO supplement of equal CHO or caloric content.

An Integrated Hardware Array for Very High Speed Logic Simulation

A hardware architecture is proposed which allows direct mapping of design simulation topology onto an acceleration platform. In order to clarify architectural principles, the simulation is confined to functional verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural innovation reduces logic complexity and execution time of boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

Structural Optimization With Nonlinear Goal Programming Using Powell’s Method

This paper presents a method for solving structural optimization problems using nonlinear goal programming techniques. The developed method removes the difficulty of having to define an objective function and constraints. It also has the capacity of handling rank ordered design objectives or goals. The formulation of the structural optimization problem into a goal programming form is discussed. The resulting optimization problem is solved using Powell’s conjugate direction search algorithm. To demonstrate the effectiveness of the method, as a design tool, the solutions of some numerical test cases are included.