Stress Test of Cascode Switch Using SiC Static Induction Transistor

Stress tests were conducted for the cascode switch using the SiC buried gate static induction transistor (SiC-BGSIT). The stress of the reverse overshoot voltage was periodically applied to the pn junction between the gate terminal and source one in the BGSIT in the cascode with pulses of 40kHz for 202 hours. This simulates the stress which can be occurred in the channel region of the BGSIT during the turn-off and turn-on operation with a parasitic inductance in the interconnection of the cascode package. The result of the stress tests has revealed that there is no significant difference between the electrical characteristics of the BGSIT cascode sample before the stress and those after the stress. Thus, the BGSIT cascode can guarantee high reliability against the stress. The result from the drain current DLTS suggests that no deferent kind of defect is created in the channel region of the BGSIT by the stress.

High Workfunction, Compound Gate Metal Engineering for Low DIBL, High Gain, High Density Advanced RF Power Static Induction Transistor (SIT) and HV Schottky Diode in 4H Silicon Carbide

Wide bandgap semiconductors, such as 4H SiC, are suitable for power regulating devices, due to compatibility with conventional process integration, high breakdown voltage and thermal conductivity [1]. For RF applications, in order to achieve better switching speed, high cut off frequency, and low series resistance (Rdson), it is essential to choose the right gate metals [2]. Engineering of the gate metals not only improves the critical device parameters by adjustment of the metal workfunction, but also affects how the high aspect ratio trenches are filled for a next generation SIT device configuration [3] - [5].

IMPROVED PROCESS FLOW FOR FORMATION OF BIPOLAR STATIC INDUCTION TRANSISTOR

The improved process flow differs from the known ones in the fact that the same photomask is used for formation of a channel stopper and metal contacts. Such approach has made it possible not only to decrease a number of the used phototomasks but it has also permitted to obtain a device with the required electrical characteristics. The paper presnts results of device and process simulation of bipolar static induction transistor (BSIT) manufactured in accordance with the improved process flow, measuring data of electrophysical parameters of its experimental samples and also comparison of simulation results with experimental data. At present there is a large quantity of software products that permit to perform physico-topological simulation of semiconductor structures. The device-process simulation is considered as a part of such simulation and it allows prior to obtaining experimental samples to determine process flow parameters at which the investigated structure will have necessary electrical parameters and characteristics. Thus the device-process simulation represents a certain “virtual production” for manufacturing semiconductor devices and microcircuits beginning from the startup stage of semiconductor wafer at production site and finishing by electrical characteristics measurements of the obtained structure. The BSIT device simulation being an analog of direct measurements of current-voltage characteristics has been performed with help of program system MOD-1D developed by the author. The BSIT model based on the fundamental system of semiconductor equations is mainly used for calculation of the BSIT current-voltage characteristics direct branch and its parameters and charge carrier recombination is described by Shockley – Read – Hall expression and equation depicting the Auger recombination process.