Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes

Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the viable solutions toward scaling down below sub-7nm technology nodes. In this work, we compare electrical performance, including variability studies of several horizontal nanosheet transistors toward transistor structure optimization. We explore the impacts of nanosheet width and thickness on the electrical performance and outline important design guidelines necessary for vertically stacked nanosheet FETs. An increase in the complexity of the stacked nanosheet structures can lead to significant device variability. Using numerical simulation, we study the characteristics fluctuations induced by the random discrete dopants (RDD) and metal grain granularity (MGG) in nanosheet gate-all-around (GAA) transistors. We use 3-D quantum-mechanically corrected transport models in the simulation. It is observed that the σVTH due to MGG variability is 12% higher than RDD variability while the RDD variability strongly influences the ION. The statistical simulation results predict that the presence of combined variability due to RDD and MGG strongly influences the threshold voltage variation (σVTH) in nanoscale devices. This approach may be applied to the different types of variability, the geometry of the device, including the vertical and lateral dimensions of the transistor, and biasing conditions.