Electromechanical Displacement of Soft/Hard PZT Bi-Layer Composite Actuator

PZTs can be classified into two types, i.e., soft and hard PZTs, which are categorized by the piezoelectric and ferroelectric properties such as coercive field, piezoelectric strain, mechanical quality factor etc. It is known that the combination effect of the soft/hard PZT composites can generate large strain/actuation compared to monolithic PZT ceramics. In this study, soft and hard PZT powders were co-pressed into bi-layer disks with various ratios between soft and hard PZT powders, ranging from 0:100~100:0 vol. % (with 10 % increments) and then they were co-sintered. Due to the difference in the planar shrinkage of the two layers and thermal expansion coefficient mismatch, dome-shaped bi-layer composites with various dome heights were obtained. It was shown that the constrained layer either soft PZT or hard PZT affected various properties including the dome geometry, the strain-E-field response, and the displacement hysteresis loop. The electromechanical properties and actuation performance of such bi-layer composite actuators have been investigated and compared to the soft and hard PZT single layer counterparts.

Multilayered Ceramic Composites – A Review

Fracture toughness enhancement of ceramic materials through multilayered ceramic composites has been developed since 1990. Toughening mechanisms are based mainly on delamination, deflection, bifurcation or crack arrest effect. Delamination and crack deflection occur by means of weak interfaces. Bifurcation (and deflection as well) and crack arrest effects are result of residual stresses arising from the thermal expansion coefficient mismatch or phase transformation on alternating layers. The main manufacturing methods of these composites are slip casting of two ceramic materials, and stacking and pressing of ceramic tapes obtained by tape casting or rolling technics, followed by suitable sintering process. This review aims to present general aspects of research performed around the theme so far. It is verified that occurs the enhancement of ceramic toughness and reliability with this technic, so it is possible to enlarge its range of application in engineering.

Thermal Effects Analysis of Flip Chip LED Packages with through Silicon via (TSV) by Using Numerical Simulation

With advancement of technology, package sizes and products are becoming smaller due to miniaturization. Separate light-emitting diode (LED) chips and control integrated circuits with through silicon via (TSV) structurescan be combined to achieve reduced size. LED chipswithFlip Chip structureare capable of higher optical efficiency and heat dissipation. Analysis of LED chip structure after heat-related destruction of the chip indicated that the chip suffered stress from heating and cooling. The material used for TSV structures is copper, sincethis provides good electrical conductivity and high thermal conductivity. However, the thermal expansion coefficient of copper is higher than for other materials and can result in thermal expansion coefficient mismatch. Hence, the use of this material is likely to cause stress concentration and thus cause damage. In this study, molybdenum and tungsten were tested as replacements for copper in TSV, and the modified TSV was subjected to simulation analysis.The results indicate that replacement of TSV materials can reduce thermal expansion coefficient mismatch and consequent stress fracture and that the performance of different materials can be simulated by Fatigue Analysis and Load.

Experimental Study of the Packaging Failure for Optical Fiber Arrays

Optical fiber array is a key component in the assembly of planar optical waveguide devices and enable greater channel counts than previously. However, assembling optical fiber array has been a challenge due to the stringent performance and reliability requirements posed by optical fiber communication applications. This paper investigates the causes of the failures involving the adhesive including: surface contamination, air entrapment, uneven curing, curing shrinkage; and thermal expansion coefficient mismatch.

Design and Simulation of a Micromachined CMOS Temperature Sensor

A design and simulation of a fully CMOS compatible micromachined multilayer cantilevers-based environmental thermometer are presented. The operation principle of the structure is depending on the mismatch effect of thermal expansion coefficient and the piezoresistive effect of polysilicon in CMOS process. Upon temperature variation, the deformation of the multilayer cantilever resulted from the large thermal expansion coefficient mismatch of different materials can be sensed and translated to an electrical voltage output by using a symmetric piezoresistive Wheatstone bridge. The mechanical characteristics of the device are analyzed with the extension of bi-layer Timoshenko model and the output of the read-out circuit is also simulated. The calculation and simulation show that the device with bi-direction deformation may have wide temperature range from -100 to 100°C and sensitivity about 0.15mV/°C, which fit the demand of radiosonde for environmental temperature measurement. This sensor may also have other favorable features, such as micro size, low-cost due to its working principle and compatibility with commercial CMOS process.

Growth and Characterization of AlGaN/GaN HEMT Structures on 3C-SiC/Si(111) Templates

Cubic SiC/Si (111) template is an interesting alternative for growing GaN on silicon. As compared with silicon, this substrate allows reducing the stress in GaN films due to both lower lattice and thermal expansion coefficient mismatch, and can provide better heat dissipation. In this work, we first developed the epitaxial growth of 3C-SiC films on 50mm Si(111) substrates using chemical vapor deposition. AlGaN/GaN high electron mobility transistors were grown by molecular beam epitaxy on these films. Both the structural quality and the electrical behavior of these structures show the feasibility of this approach.

EFFECTS OF THERMAL EXPANSION COEFFICIENT MISMATCH ON STRUCTURE AND ELECTRICAL PROPERTIES OF TiO2 FILM DEPOSITED ON Si SUBSTRATE

Effects of thermal expansion coefficient (CTE) mismatch on structure and electrical properties of TiO 2 film deposited on Si substrate by ion beam assistant electron beam evaporation have been investigated. Because of a high CTE mismatch between TiO 2 film and Si substrate, microcracks appeared in the TiO 2 film deposited directly on Si substrate after the as-deposited film was annealed at 600°C. In order to decrease the CTE mismatch, TiO 2 film was deposited on Si substrate which was covered by a ZrO 2 thin layer. As a result, crack–free TiO 2 film after annealed at the same temperature was obtained. Meanwhile, corresponding to the crack–free structure, the TiO 2 thin film has more stable dielectric properties and excellent I–V characteristics.