Energy-Efficient NoC-Based Systems for Real-Time Multimedia Applications using Approximate Computing

This work presents an energy-efficient NoC-based system for real-time multimedia applications employing approximate computing. The proposed video processing system, called SApp-NoC, is efficient in both energy and quality (QoS), employing a scalable NoC architecture composed of processing elements designed to accelerate the HEVC Fractional Motion Estimation (FME). Two solutions are proposed: HSApp-NoC (Heuristc-based SApp-NoC), and MLSApp-NoC (Machine Learning-based SApp-NoC). When compared to a precise solution processing 4K videos at 120 fps, HSApp-NoC and MLSApp-NoC reduce about 48.19% and 31.81% the energy consumption, at small quality reduction of 2.74% and 1.09%, respectively. Furthermore, a set of schedulability analysis is also proposed in order to guarantee the meeting of timing constraints at typical workload scenarios.

Iterative based image and video denoising by fractional block matching and transform domain filtering

This paper presents an iterative algorithm for image and video denoising which is based on fractional block-matching and transform domain filtering. We propose fractional motion estimation technique to find the most accurate similar blocks for each block of an image which improves sparsity enabling effective image denoising. By taking the advantage of blocks similarity and wavelet transform domain filtering along with weighted average function (WAF) in an iterative based manner, we achieve a higher level of sparsity and a better exploiting of blocks similarity redundancies of noisy images that increase the chance of preserving details and edges in the restored image. Since our algorithm is iterative, we can tradeoff between image denoising degree and computational complexity. In addition, we develop a video denoising algorithm based on the proposed image denoising algorithm. The simulation results of images and videos contaminated by additive white Gaussian noise demonstrate that our algorithm substantially achieves better denoising performance compared with previously published algorithms in terms of subjective and objective measures.

Iterative based image and video denoising by fractional block matching and transform domain filtering

This paper presents an iterative algorithm for image and video denoising which is based on fractional block-matching and transform domain filtering. We propose fractional motion estimation technique to find the most accurate similar blocks for each block of an image which improves sparsity enabling effective image denoising. By taking the advantage of blocks similarity and wavelet transform domain filtering along with weighted average function (WAF) in an iterative based manner, we achieve a higher level of sparsity and a better exploiting of blocks similarity redundancies of noisy images that increase the chance of preserving details and edges in the restored image. Since our algorithm is iterative, we can tradeoff between image denoising degree and computational complexity. In addition, we develop a video denoising algorithm based on the proposed image denoising algorithm. The simulation results of images and videos contaminated by additive white Gaussian noise demonstrate that our algorithm substantially achieves better denoising performance compared with previously published algorithms in terms of subjective and objective measures.

Hardware Implementation for the HEVC Fractional Motion Estimation Targeting Real-Time and Low-Energy

This paper presents an energy-aware and high-throughput hardware design for the Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) standard. An extensive software evaluation was performed to guide the hardware design. The adopted strategy mainly consists in using only the four squareshaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes in the Motion Estimation (ME). This approach reduces about 59% the total encoding time and, as a penalty, it leads to an increase of only 4% in the bit rate for the same image quality. Together with this simplification, a multiplierless approach, algebraic optimizations and low-power techniques were applied to the hardware design to reduce the hardware-resource usage and the energy consumption, maintaining a high processing rate. The architecture was described in VHDL and the synthesis results for ASIC 45nm Nangate standard cells demonstrate that the developed architecture is able to process Ultra-High Definition (UHD) 2160p videos at 60 frames per second (fps), with the lowest power consumption and the lowest hardware-resource usage among the related works.