Performance optimization methods for switched-capacitor biquadratic filters

A class of computer-aided optimization methods based on Differential Evolution (DE), Particle Swarm Optimization (PSO) and Nelder Mead algorithms applied to a switched-capacitor (SC) filter circuit design are investigated. Comparisons of these algorithms applied to a 4th order biquadratic two-channel filter bank CMOS design on 0.35 µm technology are made. The frequency responses of the biquadratic filters must match ideal responses in a finite number of iterations with a limited number of “particles”. The original and derived methods are evaluated on the base of their convergence progress and their reliability over different starting populations. An optimal design approach based on combining algorithms is derived as a more suitable and more reliable method for SC circuit optimization.

DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.

ANALYSIS OF MULTI-STAGE AND MULTI-RATE IIR SC DECIMATORS USING ISCMRATE

This paper describes an analysis of multi-stage and multi-rate IIR switched capacitor (SC) decimators using an interactive switched capacitor multi-rate compiler (ISCMRATE). Motivated by the experimental observations, the purpose of this paper is to explore a portion of characteristics for the multi-stage IIR SC decimators, with their implications in the context of a complete IIR SC filter. To overcome the limitations of conventional multi-stage IIR SC decimators, a novel solution has been introduced for the implementation of a multi-stage IIR SC circuit. Based on the statistical approach of the compiler, we provide the comparative analysis for different IIR SC decimators, including total capacitor area, capacitance spread and arbitrary anti-aliasing amplitude responses with a decimating factor in single and multi-stage building blocks. Examples are given to illustrate the practical feasibility of this compiler.