Investigations on Practical Issues in Solid Immersion Lens Based Sub-Wavelength Terahertz Imaging Technique: System Stability Verification and Interference Pattern Removal

Terahertz (THz) imaging techniques are attractive for a wide range of applications, such as non-destructive testing, biological sensing, and security imaging. We investigate practical issues in THz imaging systems based on a solid immersion lens (SIL). The system stability in terms of longitudinal misalignment of the SIL is experimentally verified by showing that the diffraction-limited sub-wavelength beam size (0.7 λ) is maintained as long as the SIL is axially located within the depth-of-focus (~13 λ) of the objective lens. The origin of the fringe patterns, which are undesirable but inevitable in THz imaging systems that use continuous waves, is analytically studied, and a method for minimizing the interference patterns is proposed. By combining two THz images obtained at different axial positions of the object and separated by λ/4, the interference patterns are significantly reduced, and the information hidden under the interference patterns is unveiled. The broad applicability of the proposed method is demonstrated by imaging objects with different surface profiles. Our work proves that the resolution of conventional THz imaging systems can easily be enhanced by simply inserting a SIL in front of the object with high tolerance in the longitudinal misalignment and provides a method enabling THz imaging for objects with different surface profiles.

A Novel Deprocessing Technique for Revealing Transistor-Level Damage on 7nm FinFET Devices

Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

Enabling EFA on Single Die

Working on wafer-level has been the only way of performing electrical failure analysis (EFA) without the need for die-packaging. The introduction of Si-interposer based 2.5D packaging, with high bandwidth memory (HBM) stacks surrounding our GPU chip, drastically increasing packaging turn around times from approximately 3 days to 3-4 weeks. Having to wait more than 3 weeks for EFA and debug work of 1st Silicon chips is a significant risk for chip bring-up. To address these challenges, this paper presents different ways of reusing the existing wafer-level EFA tool for single die EFA, and introduces a concept for a novel and dedicated single die tool. Additionally, singulated die fixturing and support windows are designed to enable the usage of a 2.45 Numerical Aperture Solid Immersion Lens, and first results from a near reticle limited 16 nm Fin-FET GPU product are also presented.